dds_vhdl.map.qmsg

数字移相信号发生器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 16:06:20 2005 " "Info: Processing started: Wed Dec 14 16:06:20 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off DDS_VHDL -c dds_vhdl " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DDS_VHDL -c dds_vhdl" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder32b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder32b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER32B-behav " "Info: Found design unit 1: ADDER32B-behav" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder32b.vhd" "ADDER32B-behav" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder32b.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER32B " "Info: Found entity 1: ADDER32B" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder32b.vhd" "ADDER32B" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder32b.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds_vhdl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dds_vhdl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS_VHDL-one " "Info: Found design unit 1: DDS_VHDL-one" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "DDS_VHDL-one" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS_VHDL " "Info: Found entity 1: DDS_VHDL" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" "DDS_VHDL" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/dds_vhdl.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg32b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg32b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG32B-behav " "Info: Found design unit 1: REG32B-behav" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg32b.vhd" "REG32B-behav" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 REG32B " "Info: Found entity 1: REG32B" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg32b.vhd" "REG32B" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg32b.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sin_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/sin_rom.vhd" "sin_rom-SYN" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/sin_rom.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sin_rom " "Info: Found entity 1: sin_rom" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/sin_rom.vhd" "sin_rom" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/sin_rom.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder10b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder10b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder10b.vhd" "ADDER10B-behav" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder10b.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder10b.vhd" "ADDER10B" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/adder10b.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg10b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg10b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "REG10B-behav" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" "REG10B" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_10_PHAS/reg10b.vhd" 3 -1 0 } }  } 0}  } {  } 0}