📄 dds_vhdl.tan.rpt
字号:
; N/A ; 143.68 MHz ( period = 6.960 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg5 ; sld_signaltap:phase|acq_trigger_in_reg[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.68 MHz ( period = 6.960 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg6 ; sld_signaltap:phase|acq_trigger_in_reg[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.68 MHz ( period = 6.960 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg7 ; sld_signaltap:phase|acq_trigger_in_reg[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.68 MHz ( period = 6.960 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg8 ; sld_signaltap:phase|acq_trigger_in_reg[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.68 MHz ( period = 6.960 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg9 ; sld_signaltap:phase|acq_trigger_in_reg[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg1 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg2 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg3 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg4 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg5 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg6 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg7 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg8 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 143.70 MHz ( period = 6.959 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg9 ; sld_signaltap:phase|acq_trigger_in_reg[9] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 144.36 MHz ( period = 6.927 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 144.89 MHz ( period = 6.902 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; CLK ; CLK ; None ; None ; None ;
; N/A ; 144.89 MHz ( period = 6.902 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 144.95 MHz ( period = 6.899 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; CLK ; CLK ; None ; None ; None ;
; N/A ; 144.95 MHz ( period = 6.899 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 145.12 MHz ( period = 6.891 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 147.36 MHz ( period = 6.786 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 148.24 MHz ( period = 6.746 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 148.74 MHz ( period = 6.723 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg0 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg1 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg2 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg3 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg4 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg5 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg6 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg7 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg8 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg9 ; sld_signaltap:phase|acq_trigger_in_reg[28] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.19 MHz ( period = 6.703 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg0 ; sld_signaltap:phase|acq_trigger_in_reg[21] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 149.19 MHz ( period = 6.703 ns ) ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg1 ; sld_signaltap:phase|acq_trigger_in_reg[21]⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -