dds_vhdl.tan.rpt

数字移相信号发生器设计

; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg7                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg8                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg9                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg0                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg1                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg2                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg3                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg4                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg5                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg6                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg7                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg8                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.41 MHz ( period = 6.973 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg9                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[7]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg0                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg1                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg2                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg3                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg4                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg5                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg6                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg7                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg8                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg9                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[8]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg0                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg1                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg2                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg3                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg4                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg5                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg6                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg7                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg8                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.62 MHz ( period = 6.963 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg9                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[5]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.68 MHz ( period = 6.960 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg0                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[2]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.68 MHz ( period = 6.960 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg1                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[2]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.68 MHz ( period = 6.960 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg2                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[2]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.68 MHz ( period = 6.960 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg3                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[2]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.68 MHz ( period = 6.960 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a7~porta_address_reg4                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[2]                                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;