dds_vhdl.tan.rpt

数字移相信号发生器设计

; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                                                                                                  ; To                                                                                                             ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 7.366 ns                         ; PWORD[1]                                                                                                                                                                                                                                              ; REG10B:u5|DOUT[9]                                                                                              ;                              ; CLK                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 13.540 ns                        ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a8~porta_address_reg9                                                                                                                  ; FOUT[2]                                                                                                        ; CLK                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 5.226 ns                         ; CLK                                                                                                                                                                                                                                                   ; CLK_DA                                                                                                         ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.827 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                          ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2]                                      ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 12.609 ns                        ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg9                                                                                                                  ; POUT[2]                                                                                                        ; CLK                          ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                                              ; altera_reserved_tdo                                                                                            ;                              ;                              ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 102.75 MHz ( period = 9.732 ns ) ; sld_signaltap:phase|sld_rom_sr:crc_rom_sr|WORD_SR[0]                                                                                                                                                                                                  ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                              ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 139.96 MHz ( period = 7.145 ns ) ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1] ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                                                                                       ;                                                                                                                ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                  ; To                                                                                                                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 139.96 MHz ( period = 7.145 ns )                    ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1]                            ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 140.02 MHz ( period = 7.142 ns )                    ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|regoutff ; sld_signaltap:phase|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[1]                            ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg0                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg1                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg2                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg3                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg4                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg5                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|ram_block3a9~porta_address_reg6                                                                                                                  ; sld_signaltap:phase|acq_trigger_in_reg[10]                                                                                                ; CLK        ; CLK      ; None                        ; None                      ; None                    ;