dds_vhdl.fit.eqn

数字移相信号发生器设计

--RB1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[9] at M4K_X17_Y11
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 2, Port B Depth: 1024, Port B Width: 2
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC);
RB1_q_a[9]_PORT_A_data_in_reg = DFFE(RB1_q_a[9]_PORT_A_data_in, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[9], SB1_ram_rom_data_reg[5]);
RB1_q_a[9]_PORT_B_data_in_reg = DFFE(RB1_q_a[9]_PORT_B_data_in, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[9]_PORT_A_address_reg = DFFE(RB1_q_a[9]_PORT_A_address, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[9]_PORT_B_address_reg = DFFE(RB1_q_a[9]_PORT_B_address, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_PORT_A_write_enable = GND;
RB1_q_a[9]_PORT_A_write_enable_reg = DFFE(RB1_q_a[9]_PORT_A_write_enable, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_write_enable = SB1L62;
RB1_q_a[9]_PORT_B_write_enable_reg = DFFE(RB1_q_a[9]_PORT_B_write_enable, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_clock_0 = GLOBAL(CLK);
RB1_q_a[9]_clock_1 = GLOBAL(A1L5);
RB1_q_a[9]_PORT_A_data_out = MEMORY(RB1_q_a[9]_PORT_A_data_in_reg, RB1_q_a[9]_PORT_B_data_in_reg, RB1_q_a[9]_PORT_A_address_reg, RB1_q_a[9]_PORT_B_address_reg, RB1_q_a[9]_PORT_A_write_enable_reg, RB1_q_a[9]_PORT_B_write_enable_reg, , , RB1_q_a[9]_clock_0, RB1_q_a[9]_clock_1, , , , );
RB1_q_a[9] = RB1_q_a[9]_PORT_A_data_out[0];

--RB1_q_b[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[9] at M4K_X17_Y11
RB1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC);
RB1_q_b[9]_PORT_A_data_in_reg = DFFE(RB1_q_b[9]_PORT_A_data_in, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[9], SB1_ram_rom_data_reg[5]);
RB1_q_b[9]_PORT_B_data_in_reg = DFFE(RB1_q_b[9]_PORT_B_data_in, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[9]_PORT_A_address_reg = DFFE(RB1_q_b[9]_PORT_A_address, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_b[9]_PORT_B_address_reg = DFFE(RB1_q_b[9]_PORT_B_address, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_PORT_A_write_enable = GND;
RB1_q_b[9]_PORT_A_write_enable_reg = DFFE(RB1_q_b[9]_PORT_A_write_enable, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_write_enable = SB1L62;
RB1_q_b[9]_PORT_B_write_enable_reg = DFFE(RB1_q_b[9]_PORT_B_write_enable, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_clock_0 = GLOBAL(CLK);
RB1_q_b[9]_clock_1 = GLOBAL(A1L5);
RB1_q_b[9]_PORT_B_data_out = MEMORY(RB1_q_b[9]_PORT_A_data_in_reg, RB1_q_b[9]_PORT_B_data_in_reg, RB1_q_b[9]_PORT_A_address_reg, RB1_q_b[9]_PORT_B_address_reg, RB1_q_b[9]_PORT_A_write_enable_reg, RB1_q_b[9]_PORT_B_write_enable_reg, , , RB1_q_b[9]_clock_0, RB1_q_b[9]_clock_1, , , , );
RB1_q_b[9] = RB1_q_b[9]_PORT_B_data_out[0];

--RB1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[5] at M4K_X17_Y11
RB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC);
RB1_q_a[9]_PORT_A_data_in_reg = DFFE(RB1_q_a[9]_PORT_A_data_in, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[9], SB1_ram_rom_data_reg[5]);
RB1_q_a[9]_PORT_B_data_in_reg = DFFE(RB1_q_a[9]_PORT_B_data_in, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[9]_PORT_A_address_reg = DFFE(RB1_q_a[9]_PORT_A_address, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[9]_PORT_B_address_reg = DFFE(RB1_q_a[9]_PORT_B_address, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_PORT_A_write_enable = GND;
RB1_q_a[9]_PORT_A_write_enable_reg = DFFE(RB1_q_a[9]_PORT_A_write_enable, RB1_q_a[9]_clock_0, , , );
RB1_q_a[9]_PORT_B_write_enable = SB1L62;
RB1_q_a[9]_PORT_B_write_enable_reg = DFFE(RB1_q_a[9]_PORT_B_write_enable, RB1_q_a[9]_clock_1, , , );
RB1_q_a[9]_clock_0 = GLOBAL(CLK);
RB1_q_a[9]_clock_1 = GLOBAL(A1L5);
RB1_q_a[9]_PORT_A_data_out = MEMORY(RB1_q_a[9]_PORT_A_data_in_reg, RB1_q_a[9]_PORT_B_data_in_reg, RB1_q_a[9]_PORT_A_address_reg, RB1_q_a[9]_PORT_B_address_reg, RB1_q_a[9]_PORT_A_write_enable_reg, RB1_q_a[9]_PORT_B_write_enable_reg, , , RB1_q_a[9]_clock_0, RB1_q_a[9]_clock_1, , , , );
RB1_q_a[5] = RB1_q_a[9]_PORT_A_data_out[1];

--RB1_q_b[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[5] at M4K_X17_Y11
RB1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC);
RB1_q_b[9]_PORT_A_data_in_reg = DFFE(RB1_q_b[9]_PORT_A_data_in, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[9], SB1_ram_rom_data_reg[5]);
RB1_q_b[9]_PORT_B_data_in_reg = DFFE(RB1_q_b[9]_PORT_B_data_in, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[9]_PORT_A_address_reg = DFFE(RB1_q_b[9]_PORT_A_address, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_b[9]_PORT_B_address_reg = DFFE(RB1_q_b[9]_PORT_B_address, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_PORT_A_write_enable = GND;
RB1_q_b[9]_PORT_A_write_enable_reg = DFFE(RB1_q_b[9]_PORT_A_write_enable, RB1_q_b[9]_clock_0, , , );
RB1_q_b[9]_PORT_B_write_enable = SB1L62;
RB1_q_b[9]_PORT_B_write_enable_reg = DFFE(RB1_q_b[9]_PORT_B_write_enable, RB1_q_b[9]_clock_1, , , );
RB1_q_b[9]_clock_0 = GLOBAL(CLK);
RB1_q_b[9]_clock_1 = GLOBAL(A1L5);
RB1_q_b[9]_PORT_B_data_out = MEMORY(RB1_q_b[9]_PORT_A_data_in_reg, RB1_q_b[9]_PORT_B_data_in_reg, RB1_q_b[9]_PORT_A_address_reg, RB1_q_b[9]_PORT_B_address_reg, RB1_q_b[9]_PORT_A_write_enable_reg, RB1_q_b[9]_PORT_B_write_enable_reg, , , RB1_q_b[9]_clock_0, RB1_q_b[9]_clock_1, , , , );
RB1_q_b[5] = RB1_q_b[9]_PORT_B_data_out[1];


--RB1_q_a[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[8] at M4K_X17_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
RB1_q_a[8]_PORT_A_data_in_reg = DFFE(RB1_q_a[8]_PORT_A_data_in, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[8], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[2]);
RB1_q_a[8]_PORT_B_data_in_reg = DFFE(RB1_q_a[8]_PORT_B_data_in, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[8]_PORT_A_address_reg = DFFE(RB1_q_a[8]_PORT_A_address, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[8]_PORT_B_address_reg = DFFE(RB1_q_a[8]_PORT_B_address, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_PORT_A_write_enable = GND;
RB1_q_a[8]_PORT_A_write_enable_reg = DFFE(RB1_q_a[8]_PORT_A_write_enable, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_write_enable = SB1L62;
RB1_q_a[8]_PORT_B_write_enable_reg = DFFE(RB1_q_a[8]_PORT_B_write_enable, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_clock_0 = GLOBAL(CLK);
RB1_q_a[8]_clock_1 = GLOBAL(A1L5);
RB1_q_a[8]_PORT_A_data_out = MEMORY(RB1_q_a[8]_PORT_A_data_in_reg, RB1_q_a[8]_PORT_B_data_in_reg, RB1_q_a[8]_PORT_A_address_reg, RB1_q_a[8]_PORT_B_address_reg, RB1_q_a[8]_PORT_A_write_enable_reg, RB1_q_a[8]_PORT_B_write_enable_reg, , , RB1_q_a[8]_clock_0, RB1_q_a[8]_clock_1, , , , );
RB1_q_a[8] = RB1_q_a[8]_PORT_A_data_out[0];

--RB1_q_b[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_b[8] at M4K_X17_Y10
RB1_q_b[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
RB1_q_b[8]_PORT_A_data_in_reg = DFFE(RB1_q_b[8]_PORT_A_data_in, RB1_q_b[8]_clock_0, , , );
RB1_q_b[8]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[8], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[2]);
RB1_q_b[8]_PORT_B_data_in_reg = DFFE(RB1_q_b[8]_PORT_B_data_in, RB1_q_b[8]_clock_1, , , );
RB1_q_b[8]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_b[8]_PORT_A_address_reg = DFFE(RB1_q_b[8]_PORT_A_address, RB1_q_b[8]_clock_0, , , );
RB1_q_b[8]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_b[8]_PORT_B_address_reg = DFFE(RB1_q_b[8]_PORT_B_address, RB1_q_b[8]_clock_1, , , );
RB1_q_b[8]_PORT_A_write_enable = GND;
RB1_q_b[8]_PORT_A_write_enable_reg = DFFE(RB1_q_b[8]_PORT_A_write_enable, RB1_q_b[8]_clock_0, , , );
RB1_q_b[8]_PORT_B_write_enable = SB1L62;
RB1_q_b[8]_PORT_B_write_enable_reg = DFFE(RB1_q_b[8]_PORT_B_write_enable, RB1_q_b[8]_clock_1, , , );
RB1_q_b[8]_clock_0 = GLOBAL(CLK);
RB1_q_b[8]_clock_1 = GLOBAL(A1L5);
RB1_q_b[8]_PORT_B_data_out = MEMORY(RB1_q_b[8]_PORT_A_data_in_reg, RB1_q_b[8]_PORT_B_data_in_reg, RB1_q_b[8]_PORT_A_address_reg, RB1_q_b[8]_PORT_B_address_reg, RB1_q_b[8]_PORT_A_write_enable_reg, RB1_q_b[8]_PORT_B_write_enable_reg, , , RB1_q_b[8]_clock_0, RB1_q_b[8]_clock_1, , , , );
RB1_q_b[8] = RB1_q_b[8]_PORT_B_data_out[0];

--RB1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[2] at M4K_X17_Y10
RB1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
RB1_q_a[8]_PORT_A_data_in_reg = DFFE(RB1_q_a[8]_PORT_A_data_in, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[8], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[2]);
RB1_q_a[8]_PORT_B_data_in_reg = DFFE(RB1_q_a[8]_PORT_B_data_in, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_PORT_A_address = BUS(H1_DOUT[0], H1_DOUT[1], H1_DOUT[2], H1_DOUT[3], H1_DOUT[4], H1_DOUT[5], H1_DOUT[6], H1_DOUT[7], H1_DOUT[8], H1_DOUT[9]);
RB1_q_a[8]_PORT_A_address_reg = DFFE(RB1_q_a[8]_PORT_A_address, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_address = BUS(TB1_safe_q[0], TB1_safe_q[1], TB1_safe_q[2], TB1_safe_q[3], TB1_safe_q[4], TB1_safe_q[5], TB1_safe_q[6], TB1_safe_q[7], TB1_safe_q[8], TB1_safe_q[9]);
RB1_q_a[8]_PORT_B_address_reg = DFFE(RB1_q_a[8]_PORT_B_address, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_PORT_A_write_enable = GND;
RB1_q_a[8]_PORT_A_write_enable_reg = DFFE(RB1_q_a[8]_PORT_A_write_enable, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_write_enable = SB1L62;
RB1_q_a[8]_PORT_B_write_enable_reg = DFFE(RB1_q_a[8]_PORT_B_write_enable, RB1_q_a[8]_clock_1, , , );
RB1_q_a[8]_clock_0 = GLOBAL(CLK);
RB1_q_a[8]_clock_1 = GLOBAL(A1L5);
RB1_q_a[8]_PORT_A_data_out = MEMORY(RB1_q_a[8]_PORT_A_data_in_reg, RB1_q_a[8]_PORT_B_data_in_reg, RB1_q_a[8]_PORT_A_address_reg, RB1_q_a[8]_PORT_B_address_reg, RB1_q_a[8]_PORT_A_write_enable_reg, RB1_q_a[8]_PORT_B_write_enable_reg, , , RB1_q_a[8]_clock_0, RB1_q_a[8]_clock_1, , , , );
RB1_q_a[2] = RB1_q_a[8]_PORT_A_data_out[3];

--RB1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[3] at M4K_X17_Y10
RB1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
RB1_q_a[8]_PORT_A_data_in_reg = DFFE(RB1_q_a[8]_PORT_A_data_in, RB1_q_a[8]_clock_0, , , );
RB1_q_a[8]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[8], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[2]);