a86_ip.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_ip(
  rst,clk,
  take_jmp,
  stall_ip,
  din,
  ip,ip_next,
  icode
);

input rst;
wire rst;

input clk;

input take_jmp;
input stall_ip;


input [15:0] din;

output [15:0] ip;
reg [15:0] ip; 

output [15:0] ip_next;
reg [15:0] ip_next; 

reg [15:0] ip_next_i; 

input [`a86_icode_width-1:0] icode;
wire [`a86_icode_width-1:0] icode;

reg was_reset;

// Always have next location

// Prepare relocation as 
reg [15:0] rel_value;

always @ (icode,take_jmp) 
  if (take_jmp) rel_value[7:0] = icode[`a86_icode_i_start+15:`a86_icode_i_start+8]; 
  else rel_value[7:0] = 8'h00;

always @ (icode,take_jmp) 
  if (icode[`a86_icode_i_start+15] & take_jmp) 
    rel_value[15:8] = 8'hFF; 
  else
    rel_value[15:8] = 8'h00; 


always @ (ip,icode) 
  // Branch add relative
  // Load (jump/call)
  // increment by size
  if (icode[`a86_icode_jr]) ip_next_i = ip + rel_value + 2;
  else if (icode[`a86_icode_ip_wr]) ip_next_i = icode[`a86_icode_i_start+23:`a86_icode_i_start+8];
       else ip_next_i = ip + icode[`a86_icode_instr_size+2:`a86_icode_instr_size];

always @ (ip,ip_next,stall_ip) 
  if (stall_ip) ip_next = ip;
  else ip_next = ip_next_i;

// Latch writes to ip
always @ (posedge clk) begin
  if (rst) ip <= 16'h0000;
  else if (!stall_ip) ip <= `a86_d_ip_update ip_next_i;
end


endmodule