a86_ml300_top.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "a86_defines.v"

module a86_ml300_top(

sys_clk_raw,system_reset,

ip,cs,

iobus_addr,
iobus_clk,
iobus_rst,
iobus_we,
iobus_ce,
iobus_be,
iobus_data_out,
iobus_data_in,
iobus_busy

);

input sys_clk_raw;
input system_reset;

output [15:0] ip;
wire [15:0] ip;

output [15:0] cs;
wire [15:0] cs;

wire [71:0] code;

//
output iobus_clk;
output iobus_rst;
output iobus_we;
output iobus_ce;
output [`a86_io_awidth-1:0] iobus_addr;
output [1:0] iobus_be;
output [`a86_io_dwidth-1:0] iobus_data_out;

input [`a86_io_dwidth*`a86_io_num_devices-1:0] iobus_data_in;
input [`a86_io_num_devices-1:0] iobus_busy;

assign  cs[7:0] = code[7:0];

a86_verilog_top a86_cpu (
    .rst(system_reset), 
    .clk(sys_clk_raw), 
    .debug( ), 
    .dbg_code( code ), 
    .ip(ip), 
    .sp(), 
    .bp(), 
    .si(), 
    .di(), 
    .cs(), 
    .ds(), 
    .ss(), 
    .es(), 
    .ax(), 
    .bx(), 
    .cx(), 
    .dx(), 
    .flags(), 
    .a(), 
    .aluresult(),

    .iobus_clk(iobus_clk), 
    .iobus_rst(iobus_rst), 

    .iobus_we(iobus_we), 
    .iobus_ce(iobus_ce), 

    .iobus_addr(iobus_addr), 
    .iobus_be(iobus_be), 
    .iobus_data_out(iobus_data_out), 
    .iobus_data_in(iobus_data_in), 
    .iobus_busy(iobus_busy)

    );


a86_bios_cache bios (
    .clk(sys_clk_raw), 
    .addr( ip ), 
    .lock(  ), 
    .prefix( ), 
    .code( code )
    );


endmodule