a86_fetch_block.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_fetch_block(rst,clk

,debug
,dbg_code

,icode
,opcode
,addrmode
,immed32

);

input rst;
wire rst;

input clk;
wire clk;

input debug;
wire debug;

input [63:0] dbg_code;
wire [63:0] dbg_code;

output [`a86_icode_width-1:0] icode;
wire [`a86_icode_width-1:0] icode;

output [7:0] opcode;
wire [7:0] opcode;

output [7:0] addrmode;
wire [7:0] addrmode;

output [31:0] immed32;
wire [31:0] immed32;

wire [7:0] i0;
wire [7:0] i1;
wire [7:0] i2;
wire [7:0] i3;
wire [7:0] i4;
wire [7:0] i5;

`ifdef xxx_x
 
a86_ifetch a86_ifetch_0 (
    .clk( clk ), 
    .empty( ), 
    .i0( i0 ), 
    .i1( i1 ), 
    .i2( i2 ), 
    .i3( i3 ), 
    .i4( i4 ), 
    .i5( i5 )
    );

`endif

a86_idecoder a86_idecoder_0 (
    .clk( clk ), 
    .empty( ), 
    .i0( i0 ), 
    .i1( dbg_code[7:0] ), 
    .i2( dbg_code[15:8] ), 
    .i3( dbg_code[23:16] ), 
    .i4( dbg_code[31:24] ), 
    .i5( dbg_code[39:32] ), 
    .opcode( opcode ), 
    .addrmode( addrmode ), 
    .data16( immed32[15:0] ), 
    .data16_hi( immed32[31:16] ), 
    .icode( icode )
    );






endmodule