a86_alu_block.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_alu_block(

rst,clk,icode

,ain,bin
,cx
,cx_zero

,flags
,condition
,dout

);


input rst;
wire rst;

input clk;
wire clk;

input [`a86_icode_width-1:0] icode;
wire [`a86_icode_width-1:0] icode;


input [15:0] ain;
wire [15:0] ain;

input [15:0] bin;
wire [15:0] din;

input [15:0] cx;
wire [15:0] cx;

input cx_zero;
wire cx_zero;


output [31:0] dout;
wire [31:0] dout;

output [15:0] flags;
wire [15:0] flags;

output condition;
wire condition;

wire [15:0] segment;
wire [15:0] offset;
wire [15:0] ea;


a86_alu a86_alu_0 (
    .icode( icode ),
    .ain( ain ), 
    .bin( bin ), 
    .dout( dout[15:0] ), 
    .fin( ), 
    .fout( flags ), 
    .aluop( icode[7:0] ),
    .dout_hi( dout[31:16] )
    );

a86_shifter a86_shifter_0 (
    .shop( icode[7:0] ), 
    .cl( cx[7:0] ) , 
    .imm8( icode[7:0] ), 
    .cin( ), 
    .cout( ), 
    .din( ), 
    .dout( )
    );

a86_cond_sel a86_cond_sel_0 (
    .sel( icode[4:0] ), 
    .fin( flags ), 
    .cin( ), 
    .cx_zero( cx_zero ), 
    .cout( condition )
    );


a86_flags a86_flags (
    .clk( clk ), 
    .we( icode[1] ), 
    .wmask(  ), 
    .outmask(  ), 
    .outval(  ), 
    .din(  ), 
    .flags(  )
    );




endmodule