a86_alu_bmux.v

intel 8088 架构的verilog代码

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_alu_bmux(
  rst,clk,icode,
  mem_in,
  io_in,
  dout
  );

input rst;
input clk;
input [`a86_icode_width-1:0] icode;

wire rst;
wire clk;
wire [`a86_icode_width-1:0] icode;

input [15:0] mem_in;
input [15:0] io_in;
output [15:0] dout;
reg [15:0] dout;

// and with enables!
reg [15:0] io_anded;
reg [15:0] const_anded;
reg [15:0] immed_anded;
reg [15:0] immed_3b_anded;


// data comes from IO Bus?
always @(io_in,icode) 
  if (icode[`a86_icode_in]) io_anded = io_in;
  else io_anded = 16'h0000;

// constant data (0/1/-1 ?)
always @(icode) 
  if (icode[`a86_icode_incdec]) begin
    if (icode[`a86_icode_i_start+3]) const_anded = 16'hffff;
    else const_anded = 16'h0001;
  end else const_anded = 16'h0000;


// data comes from immed value
always @(icode) 
  if (icode[`a86_icode_alub_immed]) 
    immed_anded = icode[`a86_icode_i_start+16+15:`a86_icode_i_start+16];
  else immed_anded = 16'h0000;

// data comes from immed value, 3 byte instruction!
always @(icode) 
  if (icode[`a86_icode_alub_immed_3b]) 
    immed_3b_anded = icode[`a86_icode_i_start+8+15:`a86_icode_i_start+8];
  else immed_3b_anded = 16'h0000;

// or them together
always @(io_anded, const_anded, immed_anded, immed_3b_anded)
  dout = io_anded | const_anded | immed_anded | immed_3b_anded;


endmodule