a86_verilog_top.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 286 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_verilog_top(
  rst,clk,
  debug,dbg_code,
  ip,ip_next,
  sp,bp,si,di,
  cs,ds,ss,es,
  ax,bx,cx,dx,flags,
  a,aluresult,
  icode,
  stalled,
//
// I/O  Bus
// 
  iobus_addr,iobus_clk,iobus_rst,iobus_we,iobus_ce,iobus_be,
  iobus_data_out,iobus_data_in,iobus_busy

);

input rst;
wire rst;

input clk;
wire clk;

input debug;
wire debug;

input [63:0] dbg_code;
wire [63:0] dbg_code;

output [15:0] ip;
wire [15:0] ip;

output [15:0] ip_next;
wire [15:0] ip_next;

output stalled;
reg stalled;

output [15:0] sp;
wire [15:0] sp;

output [15:0] bp;
wire [15:0] bp;

output [15:0] si;
wire [15:0] si;

output [15:0] di;
wire [15:0] di;

output [15:0] cs;
wire [15:0] cs;

output [15:0] ds;
wire [15:0] ds;

output [15:0] ss;
wire [15:0] ss;

output [15:0] es;
wire [15:0] es;

output [15:0] ax;
wire [15:0] ax;

output [15:0] bx;
wire [15:0] bx;

output [15:0] cx;
wire [15:0] cx;

output [15:0] dx;
wire [15:0] dx;

output [15:0] flags;
wire [15:0] flags;

output [19:0] a;
wire [19:0] a;

output [31:0] aluresult;
wire [31:0] aluresult;

output [`a86_icode_width-1:0] icode;
wire [`a86_icode_width-1:0] icode;

wire cx_zero;
wire condition;


wire [7:0] opcode;
wire [7:0] addrmode;
wire [31:0] immed32;

wire [15:0] alu_a;
wire [15:0] alu_b;

wire [15:0] io_2_core;

//always @(icode) cs = icode[15:0];

reg stall_ip;
wire take_jmp;



// IO Bus

output iobus_clk;
output iobus_rst;
output iobus_we;
output iobus_ce;

output [`a86_io_awidth-1:0] iobus_addr;
output [1:0] iobus_be;
output [`a86_io_dwidth-1:0] iobus_data_out;
input [`a86_io_dwidth*`a86_io_num_devices-1:0] iobus_data_in;
input [`a86_io_num_devices-1:0] iobus_busy;


wire iobus_we;
wire iobus_ce;

wire iobus_clk;
wire iobus_rst;
wire iobus_busy2core;

wire [`a86_io_awidth-1:0] iobus_addr;
wire [1:0] iobus_be;
wire [`a86_io_dwidth-1:0] iobus_data_out;
wire [`a86_io_dwidth*`a86_io_num_devices-1:0] iobus_data_in;
wire [`a86_io_num_devices-1:0] iobus_busy;

wire [15:0] core_data_out;

















reg stall;
reg [2:0] stall_cnt;

always @ (posedge clk) 
  if (rst) 
    stall_cnt <= 3'b000;
  else 
    stall_cnt <= stall_cnt + 3'b001;

always @ (stall_cnt) 
  stall_ip = stall_cnt[1];

//always @ (stall_ip) stalled = stall_ip;


always @ (iobus_busy2core) 
  stalled = iobus_busy2core;

a86_alu_block a86_alu_block_0 (
    .rst( rst ), 
    .clk( clk ), 
    .icode( icode ), 
    .ain( alu_a ), 
    .bin( alu_b ), 
    .cx( cx ), 
    .cx_zero( cx_zero ), 
    .flags( flags ), 
    .condition( condition ),
    .dout( aluresult ) 
    );

a86_alu_bmux a86_alu_bmux_0 (
    .rst( rst ), 
    .clk( clk ), 
    .icode( icode ), 
    .mem_in( 16'h0005 ), 
    .io_in( io_2_core ), 
    .dout( alu_b ) 
    );

a86_fetch_block a86_fetch_block_0 (
    .rst( rst ), 
    .clk( clk ), 
    .debug( debug ), 
    .dbg_code( dbg_code ), 
    .icode( icode ), 
    .opcode( opcode ), 
    .addrmode( addrmode ), 
    .immed32( immed32 )
    );

a86_reg_block a86_reg_block_0 (
    .rst( rst ), 
    .clk( clk ), 
    .icode( icode ), 
    .din( aluresult ), 
    .ip( ip ), 
    .ip_next( ip_next ), 
    .take_jmp ( take_jmp ),
    .stall_ip( stalled ),
    .sp( sp ), 
    .bp( bp ), 
    .si( si ), 
    .di( di ), 
    .cs( cs ), 
    .ds( ds ), 
    .ss( ss ), 
    .es( es ), 
    .ax( ax ), 
    .bx( bx ), 
    .cx( cx ), 
    .dx( dx ), 
    .cx_zero( cx_zero )
    );

a86_reg_calc_mux a86_reg_calc_mux_0 (
    .rst( rst ), 
    .clk( clk ), 
    .icode( icode ), 
    .ip( ip ), 
    .sp( sp ), 
    .bp( bp ), 
    .si( si ), 
    .di( di ), 
    .cs( cs ), 
    .ds( ds ), 
    .ss( ss ), 
    .es( es ), 
    .ax( ax ), 
    .bx( bx ), 
    .cx( cx ), 
    .dx( dx ), 
    .dout( alu_a ), 
    .a( a ), 
    .din( immed32 )
    );



a86_io_extbus a86_io_extbus_0 (
    .rst( rst ), 
    .clk( clk ), 
    .icode( icode ), 
    .core_data( aluresult[15:0] ),  
    .core_addr( dx ), 
    .core_data_out( io_2_core ),  
    .busy2core(iobus_busy2core), 
    //
    .iobus_clk( iobus_clk ), 
    .iobus_rst( iobus_rst ), 
    .iobus_we( iobus_we ), 
    .iobus_ce( iobus_ce ), 
    .iobus_addr( iobus_addr), 
    .iobus_be( iobus_be ), 
    .iobus_data_out( iobus_data_out ), 
    .iobus_data_in( iobus_data_in ), 
    .iobus_busy( iobus_busy )
    );
  








endmodule