ml300_gpio.v

来自「intel 8088 架构的verilog代码」· Verilog 代码 · 共 78 行

// http://gforge.openchip.org/projects/a86

`include "a86_defines.v"

module ml300_gpio(
iobus_addr,
iobus_clk,
iobus_rst,
iobus_we,
iobus_ce,
iobus_be,
iobus_data_out,
iobus_data_in,
iobus_busy,

gpio,
gp_button,
gp_led

);
    

input iobus_clk;
input iobus_rst;
input iobus_we;
input iobus_ce;

input [`a86_io_awidth-1:0] iobus_addr;
input [1:0] iobus_be;
input [`a86_io_dwidth-1:0] iobus_data_in;
output [`a86_io_dwidth-1:0] iobus_data_out;
reg [`a86_io_dwidth-1:0] iobus_data_out;
output iobus_busy;


input [15:0] gp_button;
output [15:0] gp_led;
reg [15:0] gp_led;

output [31:0] gpio;
reg [31:0] gpio;
reg [31:0] gpio_r;

reg gpio_base_hit;

assign iobus_busy = 1'b0; // Ready always, we are fast 

always @(iobus_addr, iobus_ce)
  gpio_base_hit = (iobus_addr[15:8] == 0) & iobus_ce;

always @ (posedge iobus_clk) begin
  
//  if (iobus_rst) gp_led <= 16'h0000;
//  else if (iobus_we & iobus_addr[0]) gp_led[15:0] <= iobus_data_in[15:0];

  if (iobus_rst) gp_led <= 16'h0000;
  else if (gpio_base_hit & iobus_we & iobus_addr[0]) gp_led[15:0] <= iobus_data_in[15:0];

  if (iobus_rst) gpio_r[15:0] <= 16'hFFFF;
  else if (gpio_base_hit & iobus_we & iobus_addr[1]) gpio_r[15:0] <= iobus_data_in;
end

// send out GPIO
always @ (gpio_r) 
  gpio[15:0] = gpio_r[15:0];


// Read buttons!
always @ (gp_button,gpio_base_hit) 
  if (gpio_base_hit) iobus_data_out = gp_button;
  else iobus_data_out = 16'h0000;





endmodule