mpc8xx.h

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//---------------------------------------------------------------------------
//
//   Copyright 1997, 1998 Motorola. All Rights Reserved.
//
//   File Name:  mpc8xx.h
//
//   Purpose:
//     Definition of the internal memory map.
//
//---------------------------------------------------------------------------


#ifndef __MPC8XX__
#define __MPC8XX__


/*****************************************************************
    MPC8xx partnum values to distinguish processor type
*****************************************************************/

#define MPC821_PARTNUM      0x00
#define MPC823_PARTNUM      0x20
#define MPC860_PARTNUM      0x00

#ifndef ASM_ONLY

#define Is823(n)    ((n) == MPC823_PARTNUM)

#endif


#ifndef ASM_ONLY

struct smc_regs {
    volatile unsigned short smc_smcmr;  /* SMC mode reg */
    volatile unsigned char  RESERVED34[0x2]; /* Reserved area */

    volatile unsigned char  RESERVED35; /* Reserved area */
    volatile unsigned char  smc_smce;   /* SMC event reg */

    volatile unsigned char  RESERVED36[0x3]; /* Reserved area */
    volatile unsigned char  smc_smcm;   /* SMC mask reg */

    volatile unsigned char  RESERVED37[0x6]; /* Reserved area */
};


/*****************************************************************
    HDLC parameter RAM
*****************************************************************/

struct hdlc_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short  tbase;      /* TX BD base address */
    unsigned short  rbase;      /* RX BD base address */
    unsigned short  mrblr;      /* Rx buffer length */
    unsigned char   tfcr;       /* Tx function code */
    unsigned char   rfcr;       /* Rx function code */
    unsigned long   rstate;     /* Rx internal state */
    unsigned long   rptr;       /* Rx internal data pointer */
    unsigned short  rcount;     /* Rx internal byte count */
    unsigned short  rbptr;      /* rb BD Pointer */
    unsigned long   rtemp;      /* Rx temp */
    unsigned long   tstate;     /* Tx internal state */
    unsigned long   tptr;       /* Tx internal data pointer */
    unsigned short  tcount;     /* Tx byte count */
    unsigned short  tbptr;      /* Tx BD pointer */
    unsigned long   ttemp;      /* Tx temp */
    unsigned long   rcrc;       /* temp receive CRC */
    unsigned long   tcrc;       /* temp transmit CRC */

    /*
     * HDLC specific parameter RAM
     */
    unsigned char   RESERVED1[4];   /* Reserved area */
    unsigned long   c_mask;     /* CRC constant */
    unsigned long   c_pres;     /* CRC preset */
    unsigned short  crcec;      /* CRC error counter */
    unsigned short  disfc;      /* discarded frame counter */
    unsigned short  nmarc;      /* nonmatching address rx cnt */
    unsigned short  abtsc;      /* abort sequence counter */
    unsigned short  mflr;       /* maximum frame length reg */
    unsigned short  retrc;      /* frame retransmission cnt */
    unsigned short  rfthr;      /* received frames threshold */
    unsigned short  max_cnt;    /* maximum length counter */
    unsigned short  hmask;      /* user defined frm addr mask */
    unsigned short  rfcnt;      /* received frames count */
    unsigned short  haddr2;     /* user defined frm address 2 */
    unsigned short  haddr1;     /* user defined frm address 1 */
    unsigned short  haddr4;     /* user defined frm address 4 */
    unsigned short  haddr3;     /* user defined frm address 3 */
    unsigned short  tmp_mb;     /* temp */
    unsigned short  tmp;        /* temp */
};


/*****************************************************************
    ASYNC HDLC parameter RAM
*****************************************************************/

struct async_hdlc_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short  tbase;      /* TX BD base address */
    unsigned short  rbase;      /* RX BD base address */
    unsigned short  mrblr;      /* Rx buffer length */
    unsigned char   tfcr;       /* Tx function code */
    unsigned char   rfcr;       /* Rx function code */
    unsigned long   rstate;     /* Rx internal state */
    unsigned long   rptr;       /* Rx internal data pointer */
    unsigned short  rcount;     /* Rx internal byte count */
    unsigned short  rbptr;      /* rb BD Pointer */
    unsigned long   rtemp;      /* Rx temp */
    unsigned long   tstate;     /* Tx internal state */
    unsigned long   tptr;       /* Tx internal data pointer */
    unsigned short  tcount;     /* Tx byte count */
    unsigned short  tbptr;      /* Tx BD pointer */
    unsigned long   ttemp;      /* Tx temp */
    unsigned long   rcrc;       /* temp receive CRC */
    unsigned long   tcrc;       /* temp transmit CRC */

    /*
     * ASYNC HDLC specific parameter RAM
     */
    unsigned char   RESERVED1[4];   /* Reserved area */
    unsigned long   c_mask;     /* CRC constant */
    unsigned long   c_pres;     /* CRC preset */
    unsigned short  eof;        /* end of flag character */
    unsigned short  bof;        /* begining of flag character */
    unsigned char   RESERVED2a[2];  /* Reserved area */
    unsigned short  esc;        /* control escape character */
    unsigned short  zero;       /* zero */
    unsigned char   RESERVED2b[2];  /* Reserved area */
    unsigned short  rfthr;      /* received frames threshold */
    unsigned char   RESERVED3[2];   /* Reserved area */
    unsigned char   RESERVED4[4];   /* Reserved area */
    unsigned long   txctl_tbl;  /* Tx ctl char mapping table */
    unsigned long   rxctl_tbl;  /* Rx ctl char mapping table */
    unsigned char  RESERVED5[2];   /* Reserved area */
    unsigned short  nof;        /* Number of opening flags */
};


/*****************************************************************
    UART parameter RAM
*****************************************************************/

/*
 * bits in uart control characters table
 */
#define CC_INVALID  0x8000      /* control character is valid */
#define CC_REJ      0x4000      /* don't store char in buffer */
#define CC_CHAR     0x00ff      /* control character */

/* UART */
struct uart_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short  tbase;      /* TX BD base address */
    unsigned short  rbase;      /* RX BD base address */
    unsigned short  mrblr;      /* Rx buffer length */
    unsigned char   tfcr;       /* Tx function code */
    unsigned char   rfcr;       /* Rx function code */
    unsigned long   rstate;     /* Rx internal state */
    unsigned long   rptr;       /* Rx internal data pointer */
    unsigned short  rcount;     /* Rx internal byte count */
    unsigned short  rbptr;      /* rb BD Pointer */
    unsigned long   rx_temp;    /* Rx temp */
    unsigned long   tstate;     /* Tx internal state */
    unsigned long   tptr;       /* Tx internal data pointer */
    unsigned short  tcount;     /* Tx byte count */
    unsigned short  tbptr;      /* Tx BD pointer */
    unsigned long   ttemp;      /* Tx temp */
    unsigned long   rcrc;       /* temp receive CRC */
    unsigned long   tcrc;       /* temp transmit CRC */

    /*
     * UART specific parameter RAM
     */
    unsigned char   RESERVED1[8];   /* Reserved area */
    unsigned short  idlc;       /* rx idle counter (internal) */
    unsigned short  max_idl;    /* maximum idle characters */
    unsigned short  parec;      /* Rx parity error counter */
    unsigned short  brkcr;      /* break count register */
    unsigned short  nosec;      /* Rx noise counter */
    unsigned short  frmer;      /* Rx framing error counter */
    unsigned short  brkln;      /* Reaceive break length */
    unsigned short  brkec;      /* Rx break character counter */
    unsigned short  uaddr2;     /* address character 2 */
    unsigned short  uaddr1;     /* address character 1 */
    unsigned short  toseq;      /* Tx out of sequence char */
    unsigned short  rtemp;      /* temp storage */
    unsigned short  cc[8];      /* Rx control characters */
    unsigned short  rccr;       /* Rx control char register */
    unsigned short  rccm;       /* Rx control char mask */
    unsigned char   RESERVED2[2];   /* Reserved area */
    unsigned short  rlbc;       /* Receive last break char */
};


/*****************************************************************
    BISYNC parameter RAM
*****************************************************************/

struct bisync_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short  tbase;      /* TX BD base address */
    unsigned short  rbase;      /* RX BD base address */
    unsigned short  mrblr;      /* Rx buffer length */
    unsigned char   tfcr;       /* Tx function code */
    unsigned char   rfcr;       /* Rx function code */
    unsigned long   rstate;     /* Rx internal state */
    unsigned long   rptr;       /* Rx internal data pointer */
    unsigned short  rcount;     /* Rx internal byte count */
    unsigned short  rbptr;      /* rb BD Pointer */
    unsigned long   rtemp;      /* Rx temp */
    unsigned long   tstate;     /* Tx internal state */
    unsigned long   tptr;       /* Tx internal data pointer */
    unsigned short  tcount;     /* Tx byte count */
    unsigned short  tbptr;      /* Tx BD pointer */
    unsigned long   ttemp;      /* Tx temp */
    unsigned long   rcrc;       /* temp receive CRC */
    unsigned long   tcrc;       /* temp transmit CRC */

    /*
     * BISYNC specific parameter RAM
     */
    unsigned char   RESERVED1[4];   /* Reserved area */
    unsigned long   crcc;       /* CRC Constant Temp Value */
    unsigned short  ptcrc;      /* Preset Transmitter CRC-16/LRC */
    unsigned short  prcrc;      /* Preset Receiver CRC-16/LRC */
    unsigned short  bsync;      /* BISYNC SYNC Character */
    unsigned short  parec;      /* Receive Parity Error Counter */
    unsigned short  cc1;        /* Rx control character 1 */
    unsigned short  bdle;       /* BISYNC DLE Character */
    unsigned short  cc3;        /* Rx control character 3 */
    unsigned short  cc2;        /* Rx control character 2 */
    unsigned short  cc5;        /* Rx control character 5 */
    unsigned short  cc4;        /* Rx control character 4 */
    unsigned short  cc7;        /* Rx control character 7 */
    unsigned short  cc6;        /* Rx control character 6 */
    unsigned short  rccm;       /* Receive Control Character Mask */
    unsigned short  cc8;        /* Rx control character 8 */
};

/*****************************************************************
    IOM2 parameter RAM
    (overlaid on tx bd[5] of SCC channel[2])
*****************************************************************/

struct iom2_pram {
    unsigned short  monitor_data;   /* monitor data */
    unsigned short  ci_data;        /* ci data */
    unsigned short  rstate;     /* receiver state */
    unsigned short  tstate;     /* transmitter state */
};

/*****************************************************************
    SPI/SMC parameter RAM
    (overlaid on tx bd[6,7] of SCC channel[2])
*****************************************************************/

#define SPI_R   0x8000      /* Ready bit in BD */

struct spi_pram {
    unsigned short  tbase;      /* Tx BD Base Address */
    unsigned short  rbase;      /* Rx BD Base Address */
    unsigned short  mrblr;      /* Rx buffer length */
    unsigned char   tfcr;       /* Tx function code */
    unsigned char   rfcr;       /* Rx function code */
    unsigned long   rstate;     /* Rx internal state */
    unsigned long   rptr;       /* Rx internal data pointer */
    unsigned short  rcount;     /* Rx internal byte count */