mpc8xx.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,115 行 · 第 1/4 页

    volatile unsigned long  pip_pbpar;  /* port b pin assignment reg */

    volatile unsigned short pip_pbodr;  /* port b open drain reg */
    volatile unsigned char  RESERVED43[0x2];    /* Reserved area */

    volatile unsigned long  pip_pbdat;  /* port b data reg */
    volatile unsigned char  RESERVED44[0x18];   /* Reserved area */

/* Serial Interface */
    volatile unsigned long  si_simode;  /* SI mode register */
    volatile unsigned char  si_sicmr;   /* SI command register */
    volatile unsigned char  si_sistr;   /* SI status register */
    volatile unsigned char  RESERVED45; /* Reserved area */
    volatile unsigned char  si_sigmr;   /* SI global mode register */
    volatile unsigned char  RESERVED46[0x4]; /* Reserved area */
    volatile unsigned long  si_sicr;    /* SI clock routing */
    volatile unsigned long  si_sirp;    /* SI ram pointers */
    volatile unsigned char  RESERVED47[0x10c]; /* Reserved area */
    volatile unsigned long  si_siram[0x80];    /* SI routing ram */
    volatile unsigned short lcda_lcolr[0x100]; /* lcd color Ram for Rev A.X */
    volatile unsigned char  RESERVED48[0x1000]; /* Reserved area */

/* BASE + 0x2000: user data memory */
    volatile unsigned char  user_data_area[0x1000]; /* dual port ram area */
    volatile unsigned char  RESERVED49[0xC00];  /* Reserved area */

/* BASE + 0x3c00: PARAMETER RAM */
    union {
        struct scc_pram {
            union {
                struct hdlc_pram    h;
                struct uart_pram    u;
                struct bisync_pram  b;
                struct transparent_pram t;
                struct async_hdlc_pram  a;
                unsigned char   RESERVED50[0x80];
            } pscc;     /* scc parameter area (protocol dependent) */
            union {
                struct {
                    struct i2c_pram i2c;
                    unsigned char   RESERVED56[0x18];
                    struct idma_pram    idma1;
                } i2c_idma;
                struct {
                    struct spi_pram spi;
                    struct timer_pram   timer;
                    struct idma_pram    idma2;
                } spi_timer_idma;
                struct {
                    union {
                        smc_uart_pram u;
                        smc_trnsp_pram t;
                        centronics_pram c;
                    } psmc;
                    union {
                        struct dsp_pram dsp;
                        unsigned char modem_param[0x40];
                    }  dsp_modem;
                } smc_modem;
                struct {
                    unsigned char   RESERVED54[0x30]; 
                    struct ucode_pram   ucode;
                } pucode;
            } pothers;
        } scc;
        struct ethernet_pram    enet_scc;
        unsigned char   pr[0x100];
    } pram[4];

} IMM, *PIMM;

#define PDA IMM

//
//  Parameter RAM Defines. Refer MPC821 user manual P.16-16
//

#define PRAM_PAGE_1   0
#define PRAM_PAGE_2   1
#define PRAM_PAGE_3   2
#define PRAM_PAGE_4   3

#define PRAM_SCC1   pram[PRAM_PAGE_1].scc.pscc
#define PRAM_I2C    pram[PRAM_PAGE_1].scc.pothers.i2c_idma.i2c
#define PRAM_IDMA1  pram[PRAM_PAGE_1].scc.pothers.i2c_idma.idma1
#define PRAM_SCC2   pram[PRAM_PAGE_2].scc.pscc
#define PRAM_SPI    pram[PRAM_PAGE_2].scc.pothers.spi_timer_idma.spi
#define PRAM_TIMER  pram[PRAM_PAGE_2].scc.pothers.spi_timer_idma.timer
#define PRAM_IDMA2  pram[PRAM_PAGE_2].scc.pothers.spi_timer_idma.idma2
#define PRAM_SCC3   pram[PRAM_PAGE_3].scc.pscc
#define PRAM_SMC1   pram[PRAM_PAGE_3].scc.pothers.smc_modem.psmc
#define PRAM_DSP1   pram[PRAM_PAGE_3].scc.pothers.smc_modem.dsp_modem
#define PRAM_SCC4   pram[PRAM_PAGE_4].scc.pscc
#define PRAM_SMC2   pram[PRAM_PAGE_4].scc.pothers.smc_modem.psmc
#define PRAM_DSP2   pram[PRAM_PAGE_4].scc.pothers.smc_modem.dsp_modem


#define udata_bd_ucode  user_data_area

#endif // ASM_ONLY

//
// Define MPC8xx Special Purpose Registers
//

#define LR          8       // Link Reg.
#define PVR        287      // Processor Version Reg.
#define DEC         22      // Decrementer Reg.
#define SRR1        27      // Save/Restore Register 1
#define ICR        148      // Instruction Compare Reg.
#define DER        149      // Debug Enable Reg.
#define ICTRL      158      // Instruction Support Control Reg.
#define IC_CST     560      // I-Cache Control/Status Reg.
#define IC_ADR     561      // I-Cache Address Reg.
#define IC_DAT     562      // I-Cache Data Reg.
#define DC_CST     568      // D-Cache Control/Status Reg.
#define DC_ADR     569      // D-Cache Address Reg.
#define DC_DAT     570      // D-Cache Data Reg.
#define IMMR       638      // Internal Memory Map Reg.
#define EIE         80      // External Interrupt Enable Reg.
#define EID         81      // External Interrupt Disable Reg.


//
// Define internal register offsets from IMMR.
//

#define MEMC_BR1_OFFSET 0x108

#define MDR_OFFSET  0x17c
#define MCR_OFFSET  0x168

#define BR0_OFFSET  0x100
#define OR0_OFFSET  0x104
#define BR1_OFFSET  0x108
#define OR1_OFFSET  0x10c
#define BR2_OFFSET  0x110
#define OR2_OFFSET  0x114
#define BR3_OFFSET  0x118
#define OR3_OFFSET  0x11c
#define BR4_OFFSET  0x120
#define OR4_OFFSET  0x124
#define BR5_OFFSET  0x128
#define OR5_OFFSET  0x12c
#define BR6_OFFSET  0x130
#define OR6_OFFSET  0x134
#define BR7_OFFSET  0x138
#define OR7_OFFSET  0x13c

#define MAMR_OFFSET 0x170
#define MBMR_OFFSET 0x174
#define SCCR_OFFSET   0x280
#define PLPRCR_OFFSET 0x284
#define SIUMCR_OFFSET 0
#define SYPCR_OFFSET 4
#define RTCSC_OFFSET 0x220

#define MPTPR_OFFSET 0x178
#define TBSCR_OFFSET 0x202
#define PISCR_OFFSET 0x242

#define PA_PAR_OFFSET 0x950
#define PA_DIR_OFFSET 0x952
#define PA_DAT_OFFSET 0x954
#define PA_ODR_OFFSET 0x956

#define PC_PAR_OFFSET 0x960
#define PC_DIR_OFFSET 0x962
#define PC_DAT_OFFSET 0x964
#define PC_SO_OFFSET  0x966
#define PC_INT_OFFSET 0x96a

#define PD_PAR_OFFSET 0x970
#define PD_DIR_OFFSET 0x972
#define PD_DAT_OFFSET 0x974



// Internal Memory Controller (MEMC) Reg's
// ============================================
//
// Definitions for memory controller option registers.  These definitions
// are used by StartUp to modify the ORx_INIT_VALUE.
//

#define BR_ADDRESS_FIELD  0xFFFF8000
#define BR_ADDR_MASK      0xFFFF8000
#define BR_VALID          0x00000001
#define BR_PORT_SIZE_16   0x00000800
#define BR_PORT_SIZE_8    0x00000400


#define OR_ADDRESS_FIELD  0xFFFF8000
#define OR_ADDR_MASK_2M   0xFFE00000
#define OR_ADDR_MASK_4M   0xFFC00000
#define OR_ADDR_MASK_8M   0xFF800000
#define OR_ADDR_MASK_16M  0xFF000000

#define OR_ACS_FIELD      0x00000600
#define OR_BURST_INHIBIT  0x00000100
#define OR_SCY_FIELD      0x000000F0
#define OR_TRLX_FIELD     0x00000004
#define OR_EXT_TA         0x00000008

#define OR_ACS_CS_SAME          (0 << 9)   // CS output same time as address
#define OR_ACS_CS_QUARTER       (2 << 9)   // CS output quarter clock later
#define OR_ACS_CS_HALF          (3 << 9)   // CS output half clock later

// CLKOUT > 25MHZ

#define OR0_SCY_90NS      0x30
#define OR0_SCY_120NS     0x40
#define OR0_ACS_8M        OR_ACS_CS_QUARTER



#ifndef ASM_ONLY

//
//  Define the bit fields of the CLKR_SCCR for use in OEMInit().
//

typedef union {
  
    unsigned long AsUlong;

    struct {

        unsigned long Dfalcd     : 2;   // Additional LCD clock division factor
        unsigned long Dflcd      : 3;   // LCD clock division factor
        unsigned long Dfnh       : 3;   // High Freq division factor
        unsigned long Dfnl       : 3;   // Low Freq division factor
        unsigned long Dfbrg      : 2;   // BRGCLK division factor
        unsigned long Dfsync     : 2;   // SyncCLK division factor
        unsigned long Reserved15 : 2;
        unsigned long Ebdf       : 2;   // CLKOUT frequency
        unsigned long Reserved11 : 2;
        unsigned long Prqen      : 1;
        unsigned long Crqen      : 1;
        unsigned long Rtsel      : 1;   // MODCK[1]
        unsigned long Rtdiv      : 1;   // MODCK1 & MODCK2
        unsigned long Tbs        : 1;
        unsigned long Reserved3  : 2;
        unsigned long Com        : 2;
        unsigned long Reserved0  : 1;

    } AsFields;

} CLKR_SCCR, *PCLKR_SCCR;


//
//  Define a Baud Rate Generator Configuration Register
//

typedef union {
    
    unsigned long AsUlong;

    struct {

        unsigned long Div16     :  1;     // BRG Clock Prescalar divide by 16
        unsigned long ClkDiv    : 12;     // Clock Divider
        unsigned long AutoBaud  :  1;     // Autobaud
        unsigned long Extclk    :  2;     // External Clock Source
        unsigned long Enable    :  1;     // Enable BRG
        unsigned long Reset     :  1;     // Reset BRG
        unsigned long Reserved0 : 14;     // Reserved

    } AsFields;

} BRGCR;

#endif // ASM_ONLY


#endif  // __MPC8XX__