mpc8xx.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 1,115 行 · 第 1/4 页

    volatile unsigned char  RESERVED58c[0x3];
    volatile unsigned char  siu_sivec;  /* Interrupt vector */
    volatile unsigned long  siu_tesr;   /* Transfer error status */
    volatile unsigned char  RESERVED1[0xc];/* Reserved area */
    volatile unsigned long  dma_sdcr;   /* SDMA configuration reg */
    volatile unsigned char  RESERVED55[0x4c];

/* PCMCIA */
    volatile unsigned long  pcmcia_pbr0;    /* PCCard Base   Register 0   */
    volatile unsigned long  pcmcia_por0;    /* PCCard Option Register 0   */
    volatile unsigned long  pcmcia_pbr1;    /* PCCard Base   Register 1   */
    volatile unsigned long  pcmcia_por1;    /* PCCard Option Register 1   */
    volatile unsigned long  pcmcia_pbr2;    /* PCCard Base   Register 2   */
    volatile unsigned long  pcmcia_por2;    /* PCCard Option Register 2   */
    volatile unsigned long  pcmcia_pbr3;    /* PCCard Base   Register 3   */
    volatile unsigned long  pcmcia_por3;    /* PCCard Option Register 3   */
    volatile unsigned long  pcmcia_pbr4;    /* PCCard Base   Register 4   */
    volatile unsigned long  pcmcia_por4;    /* PCCard Option Register 4   */
    volatile unsigned long  pcmcia_pbr5;    /* PCCard Base   Register 5   */
    volatile unsigned long  pcmcia_por5;    /* PCCard Option Register 5   */
    volatile unsigned long  pcmcia_pbr6;    /* PCCard Base   Register 6   */
    volatile unsigned long  pcmcia_por6;    /* PCCard Option Register 6   */
    volatile unsigned long  pcmcia_pbr7;    /* PCCard Base   Register 7   */
    volatile unsigned long  pcmcia_por7;    /* PCCard Option Register 7   */
    volatile unsigned char  RESERVED7Ca[0x20];
    volatile unsigned long  pcmcia_pgcra;   /* General Control Register A */
    volatile unsigned long  pcmcia_pgcrb;   /* General Control Register B */
    volatile unsigned long  pcmcia_pscr;    /* Status Changed Register    */
    volatile unsigned char  RESERVED7Cb[0x4];
    volatile unsigned long  pcmcia_pipr;    /* Input Pins Register */
    volatile unsigned char  RESERVED7Cc[0x4];
    volatile unsigned long  pcmcia_per;     /* Interrupt Enable Register  */
    volatile unsigned char  RESERVED2[0x4];/* Reserved area */

/* MEMC */
    volatile unsigned long  memc_br0;   /* base register 0 */
    volatile unsigned long  memc_or0;   /* option register 0 */
    volatile unsigned long  memc_br1;   /* base register 1 */
    volatile unsigned long  memc_or1;   /* option register 1 */
    volatile unsigned long  memc_br2;   /* base register 2 */
    volatile unsigned long  memc_or2;   /* option register 2 */
    volatile unsigned long  memc_br3;   /* base register 3 */
    volatile unsigned long  memc_or3;   /* option register 3 */
    volatile unsigned long  memc_br4;   /* base register 3 */
    volatile unsigned long  memc_or4;   /* option register 3 */
    volatile unsigned long  memc_br5;   /* base register 3 */
    volatile unsigned long  memc_or5;   /* option register 3 */
    volatile unsigned long  memc_br6;   /* base register 3 */
    volatile unsigned long  memc_or6;   /* option register 3 */
    volatile unsigned long  memc_br7;   /* base register 3 */
    volatile unsigned long  memc_or7;   /* option register 3 */
    volatile unsigned char  RESERVED3[0x24];    /* Reserved area */
    volatile unsigned long  memc_mar;   /* Memory address */
    volatile unsigned long  memc_mcr;   /* Memory command */
    volatile unsigned char  RESERVED4[0x4]; /* Reserved area */
    volatile unsigned long  memc_mamr;  /* Machine A mode */
    volatile unsigned long  memc_mbmr;  /* Machine B mode */
    volatile unsigned short memc_mptpr; /* Memory periodic timer prescalar */
    volatile unsigned short memc_mstat; /* Memory status */
    volatile unsigned long  memc_mdr;   /* Memory data */
    volatile unsigned char  RESERVED5[0x80];/* Reserved area */

/* SYSTEM INTEGRATION TIMERS */
    volatile unsigned short RESERVED5A[1];  /* Reserved area */
    volatile unsigned short simt_tbscr; /* Time base stat&ctr */

    volatile unsigned long  simt_tbreff0;   /* Time base reference 0 */
    volatile unsigned long  simt_tbreff1;   /* Time base reference 1 */
    volatile unsigned char  RESERVED6[0x14];/* Reserved area */

    volatile unsigned char  RESERVED6A[0x2];/* Reserved area */
    volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */

    volatile unsigned long  simt_rtc;   /* Realtime clock */
    volatile unsigned long  simt_rtsec; /* Realtime alarm seconds */
    volatile unsigned long  simt_rtcal; /* Realtime alarm */
    volatile unsigned char  RESERVED56[0x10];/* Reserved area */

    volatile unsigned char  RESERVED56A[0x2];/* Reserved area */
    volatile unsigned short simt_piscr; /* PIT stat&ctrl */

    volatile unsigned long  simt_pitc;  /* PIT counter */
    volatile unsigned long  simt_pitr;  /* PIT */
    volatile unsigned char  RESERVED7[0x34];/* Reserved area */

/* CLOCKS, RESET */
    volatile unsigned long  clkr_sccr;  /* System clk cntrl */
    volatile unsigned long  clkr_plprcr;    /* PLL reset&ctrl */
    volatile unsigned long  clkr_rsr;   /* reset status */
    volatile unsigned long  clkr_RESERVED1[29];/* Reserved area */


/* SYSTEM INTEGRATION TIMERS AND KEYS */
    volatile unsigned long simtk_tbscrk;
    volatile unsigned long simtk_tbreff0k;
    volatile unsigned long simtk_tbreff1k;
    volatile unsigned long simtk_tbk;
    volatile unsigned long simtk_RESERVED1[4];
    volatile unsigned long simtk_rtcsck;
    volatile unsigned long simtk_rtck;
    volatile unsigned long simtk_rtseck;
    volatile unsigned long simtk_rtcalk;
    volatile unsigned long simtk_RESERVED2[4];
    volatile unsigned long simtk_piscrk;
    volatile unsigned long simtk_pitck;
    volatile unsigned long simtk_RESERVED3[14];

/* CLOCKS, RESET KEYS */
    volatile unsigned long clkrk_sccrk;
    volatile unsigned long clkrk_plprcrk;
    volatile unsigned long clkrk_rsrk;
    volatile unsigned long clkrk_RESERVED1[29];

/* UNUSED REGIONS */
    volatile unsigned long UNUSED1[0x100];
    volatile unsigned long UNUSED2[0x10];

/* LCD */
    volatile unsigned long  lcd_lccr;   /* configuration Reg */
    volatile unsigned long  lcd_lchcr;  /* Horizontal ctl Reg */
    volatile unsigned long  lcd_lcvcr;  /* Vertical ctl Reg */
    volatile unsigned char  RESERVED67[4];
    volatile unsigned long  lcd_lcfaa;  /* Frame buffer A Address */
    volatile unsigned long  lcd_lcfba;  /* Frame buffer B Address */
    volatile unsigned char  RESERVED9a[0x3];/* Reserved area */
    volatile unsigned char  lcd_lcsr;   /* Status Reg */
    volatile unsigned char  RESERVED9b[0x4];/* Reserved area */

/* I2C */
    volatile unsigned char  RESERVED59[3];
    volatile unsigned char  i2c_i2mod;  /* i2c mode */
    volatile unsigned char  RESERVED60[3];
    volatile unsigned char  i2c_i2add;  /* i2c address */
    volatile unsigned char  RESERVED61[3];
    volatile unsigned char  i2c_i2brg;  /* i2c brg */
    volatile unsigned char  RESERVED62[3];
    volatile unsigned char  i2c_i2com;  /* i2c command */
    volatile unsigned char  RESERVED63[3];
    volatile unsigned char  i2c_i2cer;  /* i2c event */
    volatile unsigned char  RESERVED10a[0x3];/* Reserved area */
    volatile unsigned char  i2c_i2cmr;  /* i2c mask */
    volatile unsigned char  RESERVED10b[0x88];/* Reserved area */

/* DMA */
    volatile unsigned char  RESERVED11[0x4];/* Reserved area */
    volatile unsigned long  dma_sdar;   /* SDMA address reg */
    volatile unsigned char  RESERVED13[0x3];/* Reserved area */
    volatile unsigned char  dma_sdsr;   /* SDMA status reg */
    volatile unsigned char  RESERVED14[0x3];/* Reserved area */
    volatile unsigned char  dma_sdmr;   /* SDMA mask reg */
    volatile unsigned char  RESERVED15[0x3];/* Reserved area */
    volatile unsigned char  dma_idsr1;  /* IDMA1 status reg */
    volatile unsigned char  RESERVED16[0x3];/* Reserved area */
    volatile unsigned char  dma_idmr1;  /* IDMA1 mask reg */
    volatile unsigned char  RESERVED17[0x3];/* Reserved area */
    volatile unsigned char  dma_idsr2;  /* IDMA2 status reg */
    volatile unsigned char  RESERVED18a[0x3];/* Reserved area */
    volatile unsigned char  dma_idmr2;  /* IDMA2 mask reg */
    volatile unsigned char  RESERVED18b[0x10];/* Reserved area */

/* CPM Interrupt Controller */
    volatile unsigned char  RESERVED19a[0x2];/* Reserved area */
    volatile unsigned short cpmi_civr;  /* CP interrupt vector reg */
    volatile unsigned char  RESERVED19b[0xc];/* Reserved area */
    volatile unsigned long  cpmi_cicr;  /* CP interrupt configuration reg */
    volatile unsigned long  cpmi_cipr;  /* CP interrupt pending reg */
    volatile unsigned long  cpmi_cimr;  /* CP interrupt mask reg */
    volatile unsigned long  cpmi_cisr;  /* CP interrupt in-service reg */

/* I/O port */
    volatile unsigned short pio_papar;  /* port A pin assignment reg */
    volatile unsigned short pio_padir;  /* port A data direction reg */
    volatile unsigned short pio_padat;  /* port A data register */
    volatile unsigned short pio_paodr;  /* port A open drain reg */
    volatile unsigned char  RESERVED20[0x8];    /* Reserved area */
    volatile unsigned short pio_pcpar;  /* port C pin assignment reg */
    volatile unsigned short pio_pcdir;  /* port C data direction reg */
    volatile unsigned short pio_pcdat;  /* port C data register */
    volatile unsigned short pio_pcso;   /* port C special options */
    volatile unsigned char  RESERVED64a[2];
    volatile unsigned short pio_pcint;  /* port C interrupt cntrl reg */
    volatile unsigned char  RESERVED64b[4];
    volatile unsigned short pio_pdpar;  /* port D pin assignment reg */
    volatile unsigned short pio_pddir;  /* port D Data Direction reg */
    volatile unsigned short pio_pddat;  /* port D data reg */
    volatile unsigned char  RESERVED65[2];
    volatile unsigned char  RESERVED21[0x8];    /* Reserved area */

/* CPM Timer */
    volatile unsigned char  RESERVED22a[0x2];   /* Reserved area */
    volatile unsigned short timer_tgcr; /* timer global configuration  reg */
    volatile unsigned char  RESERVED22b[0xc];   /* Reserved area */
    volatile unsigned short timer_tmr2; /* timer 2 mode reg */
    volatile unsigned short timer_tmr1; /* timer 1 mode reg */
    volatile unsigned short timer_trr2; /* timer 2 referance reg */
    volatile unsigned short timer_trr1; /* timer 1 referance reg */
    volatile unsigned short timer_tcr2; /* timer 2 capture reg */
    volatile unsigned short timer_tcr1; /* timer 1 capture reg */
    volatile unsigned short timer_tcn2; /* timer 2 counter reg */
    volatile unsigned short timer_tcn1; /* timer 1 counter reg */
    volatile unsigned short timer_tmr4; /* timer 4 mode reg */
    volatile unsigned short timer_tmr3; /* timer 3 mode reg */
    volatile unsigned short timer_trr4; /* timer 4 referance reg */
    volatile unsigned short timer_trr3; /* timer 3 referance reg */
    volatile unsigned short timer_tcr4; /* timer 4 capture reg */
    volatile unsigned short timer_tcr3; /* timer 3 capture reg */
    volatile unsigned short timer_tcn4; /* timer 4 counter reg */
    volatile unsigned short timer_tcn3; /* timer 3 counter reg */
    volatile unsigned short timer_ter2; /* timer 2 event reg */
    volatile unsigned short timer_ter1; /* timer 1 event reg */
    volatile unsigned short timer_ter4; /* timer 4 event reg */
    volatile unsigned short timer_ter3; /* timer 3 event reg */
    volatile unsigned char  RESERVED23[0x8];    /* Reserved area */

/* CP */
    volatile unsigned char  RESERVED24[0x2];    /* Reserved area */
    volatile unsigned short cp_cr;      /* command register */
    volatile unsigned char  cp_resv1;   /* Reserved reg */
    volatile unsigned char  RESERVED25; /* Reserved area */
    volatile unsigned short cp_rccr;    /* main configuration reg */
    volatile unsigned long  cp_resv2;   /* Reserved reg */
    volatile unsigned short cp_rctr2;   /* ram break register 2 */
    volatile unsigned short cp_rctr1;   /* ram break register 1 */
    volatile unsigned short cp_rctr4;   /* ram break register 4 */
    volatile unsigned short cp_rctr3;   /* ram break register 3 */
    volatile unsigned short cp_rter;    /* RISC timers event reg */
    volatile unsigned char  RESERVED26[0x2];    /* Reserved area */
    volatile unsigned short cp_rtmr;    /* RISC timers mask reg */
    volatile unsigned char  RESERVED27[0x2];    /* Reserved area */
    volatile unsigned char  RESERVED28[0x14];   /* Reserved area */

/* BRG */
    volatile unsigned long  brgc1;      /* BRG1 configuration reg */
    volatile unsigned long  brgc2;      /* BRG2 configuration reg */
    volatile unsigned long  brgc3;      /* BRG3 configuration reg */
    volatile unsigned long  brgc4;      /* BRG4 configuration reg */

/* SCC registers */
    struct scc_regs {
        volatile unsigned long  scc_gsmra; /* SCC general mode reg */
        volatile unsigned long  scc_gsmrb; /* SCC general mode reg */
        volatile unsigned char  RESERVED29[0x2]; /* Reserved area */
        volatile unsigned short scc_psmr;  /* protocol specific mode register */
        volatile unsigned short scc_dsr;   /* SCC data sync reg */
        volatile unsigned short scc_todr;  /* SCC transmit on demand */
        volatile unsigned char  RESERVED30[0x2];/* Reserved area */
        volatile unsigned short scc_scce;   /* SCC event reg */
        volatile unsigned char  scc_sccs;   /* SCC status reg */
        volatile unsigned char  RESERVED31[0x1];/* Reserved area */
        volatile unsigned short scc_sccm;   /* SCC mask reg */
        volatile unsigned short scc_irsip;  /* IR Serial IPCR reg */
        volatile unsigned short scc_irmode; /* IR mode reg */
        volatile unsigned char  RESERVED32[0x4]; /* Reserved area */
    } scc_regs[4];

/* SMC */
    struct smc_regs smc_regs[2];

/* SPI */
    volatile unsigned char  RESERVED38a[0x2]; /* Reserved area */
    volatile unsigned short spi_spmode;       /* SPI mode reg */
    volatile unsigned char  RESERVED39a[0x1]; /* Reserved area */
    volatile unsigned char  spi_spie;         /* SPI event reg */
    volatile unsigned char  RESERVED38b[0x2]; /* Reserved area */
    volatile unsigned char  RESERVED40a[0x1];   /* Reserved area */
    volatile unsigned char  spi_spim;   /* SPI mask reg */
    volatile unsigned char  RESERVED39b[0x2];   /* Reserved area */
    volatile unsigned char  RESERVED41a[0x2];   /* Reserved area */
    volatile unsigned char  spi_spcom;  /* SPI command reg */
    volatile unsigned char  RESERVED40b[0x1];   /* Reserved area */

/* PIP */
    volatile unsigned short pip_pipc;   /* pip configuration reg */
    volatile unsigned char  RESERVED41b[0x2];   /* Reserved area */

    volatile unsigned short pip_ptpr;   /* pip timing parameters reg */
    volatile unsigned char  RESERVED42[0x2];    /* Reserved area */

    volatile unsigned long  pip_pbdir;  /* port b data direction reg */