ar_dc.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 2,451 行 · 第 1/5 页

//    
//  $Workfile: ar_dc.h $
//  $Revision: 3 $
//
//  Description:
//
//  Last modification: 
//     $Author: Markv $ 
//     $Date: 10/19/98 3:36p $
//  
//  Trade secret of ATI Technologies, Inc.
//  Copyright 1997, ATI Technologies, Inc., (unpublished)
//
//  All rights reserved.  This notice is intended as a precaution against
//  inadvertent publication and does not imply publication or any waiver
//  of confidentiality.  The year included in the foregoing notice is the
//  year of creation of the work.
//
//


#if !defined(_AR_DC_H)
#define _AR_DC_H

//------------------------
// Register Space Mapping
//------------------------

// Configuration Register Spaces
//     CFG RS 0:  RAGE PRO Configuration Space 

// I/O Register Spaces
//     IO RS 0:   Block I/O Register Space 
//     IO RS 1:   Sparse I/O Register Space (VGA Port) 
//     IO RS 2:   Multi-function VGA I/O Space 

// Memory Mapped Register Spaces
//     MM RS 0:   Register Block in Linear Aperture 
//     MM RS 1:   Register Block in Auxilliary Aperture 
//     MM RS 2:   Register Block in VGA Aperture 
//     MM RS 3:   Multi-function Register Block in Linear Aperture 

// Internal Register Spaces

//------------------
// Block Definitions
//------------------

#define BLOCK_CORE 0

//------------------------------
// Decoder Function Prototypes
//------------------------------

USHORT cfRF_CORE_RS0_decode(USHORT, ULONG, BYTE, BYTE);
USHORT ioRF_CORE_RS0_decode(USHORT, ULONG, BYTE, BYTE);
USHORT ioRF_CORE_RS1_decode(USHORT, ULONG, BYTE, BYTE);
USHORT ioRF_CORE_RS2_decode(USHORT, ULONG, BYTE, BYTE);
USHORT mmRF_CORE_RS0_decode(USHORT, ULONG, BYTE, BYTE);
USHORT mmRF_CORE_RS1_decode(USHORT, ULONG, BYTE, BYTE);
USHORT mmRF_CORE_RS2_decode(USHORT, ULONG, BYTE, BYTE);
USHORT mmRF_CORE_RS3_decode(USHORT, ULONG, BYTE, BYTE);
USHORT RF_CORE_CRTCInd_decode(USHORT, ULONG, BYTE, BYTE);
USHORT RF_CORE_SEQInd_decode(USHORT, ULONG, BYTE, BYTE);
USHORT RF_CORE_GRAPHInd_decode(USHORT, ULONG, BYTE, BYTE);
USHORT RF_CORE_ATTRInd_decode(USHORT, ULONG, BYTE, BYTE);
USHORT RF_CORE_PLLInd_decode(USHORT, ULONG, BYTE, BYTE);

//------------------------------
// Decoder Array Prototypes
//------------------------------

typedef USHORT (*pDecodeFn) (USHORT add_mode, ULONG offset, BYTE cntl, BYTE fcntl);

extern pDecodeFn pCF_CORE_Decoder[];
extern pDecodeFn pIO_CORE_Decoder[];
extern pDecodeFn pMM_CORE_Decoder[];



//------------------------------
// Definitions
//------------------------------

// address for nonexistent regs.
#define NON_EXIST_i 0

// define all address modes
#define MODE_OFF_0 0


//----------------------------
// Register Definitions
//----------------------------

//*********************
//*** Block:  'CORE'
//*********************

// **** Configuration:  Register Definitions ****

// cfgVENDOR_ID
#define cfgVENDOR_ID_off_0 0x0100
#define cfgVENDOR_ID_i 1
#define cfgVENDOR_ID__VendorId 1


// cfgDEVICE_ID
#define cfgDEVICE_ID_off_0 0x0102
#define cfgDEVICE_ID_i 2
#define cfgDEVICE_ID__DeviceId 1


// cfgCT_CNTL
#define cfgCT_CNTL_off_0 0x0104
#define cfgCT_CNTL_i 3
#define cfgCT_CNTL__IOAccessEnable 1
#define cfgCT_CNTL__MemAccessEnable 2
#define cfgCT_CNTL__BusMasterEnable 3
#define cfgCT_CNTL__SpecialCycleEnable 4
#define cfgCT_CNTL__MemWriteInvalidateEnable 5
#define cfgCT_CNTL__PalSnoopEn 6
#define cfgCT_CNTL__ParityErrorEn 7
#define cfgCT_CNTL__ReadWaitCycleCntl 8
#define cfgCT_CNTL__SERREn 9


// cfgCT_ABORT
#define cfgCT_ABORT_off_0 0x0106
#define cfgCT_ABORT_i 4
#define cfgCT_ABORT__CapList 1
#define cfgCT_ABORT__FastBackCapable 2
#define cfgCT_ABORT__DEVSELTiming 3
#define cfgCT_ABORT__SignalTargetAbort 4
#define cfgCT_ABORT__ReceivedTargetAbort 5
#define cfgCT_ABORT__ReceivedMasterAbort 6
#define cfgCT_ABORT__SignaledSystemError 7
#define cfgCT_ABORT__ParityErrorDetect 8


// cfgREVISED_ID
#define cfgREVISED_ID_off_0 0x0108
#define cfgREVISED_ID_i 5
#define cfgREVISED_ID__VersionID 1
#define cfgREVISED_ID__FoundryID 2
#define cfgREVISED_ID__RevisionID 3


// cfgREGPROG_INF
#define cfgREGPROG_INF_off_0 0x0109
#define cfgREGPROG_INF_i 6
#define cfgREGPROG_INF__RegLevelProgInf 1


// cfgSUBCLASSPROG_INF
#define cfgSUBCLASSPROG_INF_off_0 0x010a
#define cfgSUBCLASSPROG_INF_i 7
#define cfgSUBCLASSPROG_INF__SubClassProgInf 1


// cfgBASE_CODE
#define cfgBASE_CODE_off_0 0x010b
#define cfgBASE_CODE_i 8
#define cfgBASE_CODE__BaseClassCode 1


// cfgCACHE_LINE
#define cfgCACHE_LINE_off_0 0x010c
#define cfgCACHE_LINE_i 9
#define cfgCACHE_LINE__CacheLineSize 1


// cfgLATENCY
#define cfgLATENCY_off_0 0x010d
#define cfgLATENCY_i 10
#define cfgLATENCY__LatencyTimer 1


// cfgHEADER
#define cfgHEADER_off_0 0x010e
#define cfgHEADER_i 11
#define cfgHEADER__HeaderType 1


// cfgBIST
#define cfgBIST_off_0 0x010f
#define cfgBIST_i 12
#define cfgBIST__BIST 1


// cfgAPER_BASE
#define cfgAPER_BASE_off_0 0x0110
#define cfgAPER_BASE_i 13
#define cfgAPER_BASE__ApertureBaseRsvd0 1
#define cfgAPER_BASE__PrefetchEn 2
#define cfgAPER_BASE__ApertureBaseRsvd 3
#define cfgAPER_BASE__ApertureBase 4


// cfgBLOCK_IO
#define cfgBLOCK_IO_off_0 0x0114
#define cfgBLOCK_IO_i 14
#define cfgBLOCK_IO__BlockIOBit1 1
#define cfgBLOCK_IO__BlockIOAddress 2


// cfgREG_APER_BASE
#define cfgREG_APER_BASE_off_0 0x0118
#define cfgREG_APER_BASE_i 15
#define cfgREG_APER_BASE__RegAperBaseRsvd 1
#define cfgREG_APER_BASE__RegAperBase 2


// cfgADAPTER_ID
#define cfgADAPTER_ID_off_0 0x012c
#define cfgADAPTER_ID_i 16
#define cfgADAPTER_ID__AdapterId 1


// cfgADAPTER_ID_W
#define cfgADAPTER_ID_W_off_0 0x014c
#define cfgADAPTER_ID_W_i 17
#define cfgADAPTER_ID_W__AdapterIdW 1


// cfgBIOS_ROM
#define cfgBIOS_ROM_off_0 0x0130
#define cfgBIOS_ROM_i 18
#define cfgBIOS_ROM__BiosRomEn 1
#define cfgBIOS_ROM__BiosBaseAddr 2


// cfgCAPABILITIES_PTR
#define cfgCAPABILITIES_PTR_off_0 0x0134
#define cfgCAPABILITIES_PTR_i 19
#define cfgCAPABILITIES_PTR__CapPtr 1


// cfgINTERRUPT_LINE
#define cfgINTERRUPT_LINE_off_0 0x013c
#define cfgINTERRUPT_LINE_i 20
#define cfgINTERRUPT_LINE__InterruptLine 1


// cfgINTERRUPT_PIN
#define cfgINTERRUPT_PIN_off_0 0x013d
#define cfgINTERRUPT_PIN_i 21
#define cfgINTERRUPT_PIN__InterruptPin 1


// cfgMIN_GRANT
#define cfgMIN_GRANT_off_0 0x013e
#define cfgMIN_GRANT_i 22
#define cfgMIN_GRANT__MinGnt 1


// cfgMAX_LATENCY
#define cfgMAX_LATENCY_off_0 0x013f
#define cfgMAX_LATENCY_i 23
#define cfgMAX_LATENCY__MaxLat 1


// cfgIO_BASE
#define cfgIO_BASE_off_0 0x0140
#define cfgIO_BASE_i 24
#define cfgIO_BASE__GENENA 1


// cfgCAPABILITIES_ID
#define cfgCAPABILITIES_ID_off_0 0x0150
#define cfgCAPABILITIES_ID_i 25
#define cfgCAPABILITIES_ID__CapId 1
#define cfgCAPABILITIES_ID__NextPtr 2
#define cfgCAPABILITIES_ID__AGPMinor 3
#define cfgCAPABILITIES_ID__AGPMajor 4


// cfgAGP_STATUS
#define cfgAGP_STATUS_off_0 0x0154
#define cfgAGP_STATUS_i 26
#define cfgAGP_STATUS__Rate 1
#define cfgAGP_STATUS__SBA 2
#define cfgAGP_STATUS__RQ 3


// cfgAGP_COMMAND
#define cfgAGP_COMMAND_off_0 0x0158
#define cfgAGP_COMMAND_i 27
#define cfgAGP_COMMAND__DataRate 1
#define cfgAGP_COMMAND__AGPEn 2
#define cfgAGP_COMMAND__SBAEn 3
#define cfgAGP_COMMAND__RQDepth 4


// **** I/O:  Register Definitions ****

// GENMO_RD
#define GENMO_RD_off_0 0x03cc
#define GENMO_RD_i 1
#define GENMO_RD__GenmoMonoAddressb 1
#define GENMO_RD__VGARamEnable 2
#define GENMO_RD__VGACkSel 3
#define GENMO_RD__OddEvenMdPgSel 4
#define GENMO_RD__VgaVsyncPol 5
#define GENMO_RD__VgaHsyncPol 6


// GENMO_WT
#define GENMO_WT_off_0 0x03c2
#define GENMO_WT_i 2
#define GENMO_WT__GenmoMonoAddressb 1
#define GENMO_WT__VGARamEnable 2
#define GENMO_WT__VGACkSel 3
#define GENMO_WT__OddEvenMdPgSel 4
#define GENMO_WT__HSyncPolarity 5
#define GENMO_WT__VSyncPolarity 6


// GENFC_RD
#define GENFC_RD_off_0 0x03ca
#define GENFC_RD_i 3
#define GENFC_RD__VSyncSel 1


// GENFC_WTB
#define GENFC_WTB_off_0 0x03ba
#define GENFC_WTB_i 4
#define GENFC_WTB__VSyncSel 1


// GENFC_WTD
#define GENFC_WTD_off_0 0x03da
#define GENFC_WTD_i 5
#define GENFC_WTD__VSyncSel 1


// GENS0
#define GENS0_off_0 0x03c2
#define GENS0_i 6
#define GENS0__SenseSwitch 1
#define GENS0__CRTIntr 2


// GENS1B
#define GENS1B_off_0 0x03ba
#define GENS1B_i 7
#define GENS1B__NoDisplay 1
#define GENS1B__VgaVstatus 2
#define GENS1B__PixelReadBackRd 3


// GENS1D
#define GENS1D_off_0 0x03da
#define GENS1D_i 8
#define GENS1D__DisplayEna 1
#define GENS1D__VRetraceSta 2
#define GENS1D__PixelReadBackWt 3


// GENENA
#define GENENA_off_0 0x46e8
#define GENENA_i 9
#define GENENA__VgaEnable0 1
#define GENENA__GenvsEnable 2


// GENENB
#define GENENB_off_0 0x03c3
#define GENENB_i 10
#define GENENB__VgaEnable1 1


// GENVS
#define GENVS_off_0 0x0102
#define GENVS_i 11
#define GENVS__VgaEnable2 1


// DAC_DATA
#define DAC_DATA_off_0 0x03c9
#define DAC_DATA_i 12
#define DAC_DATA__DacData 1


// DAC_MASK
#define DAC_MASK_off_0 0x03c6
#define DAC_MASK_i 13
#define DAC_MASK__DacMask 1


// DAC_R_INDEX
#define DAC_R_INDEX_off_0 0x03c7
#define DAC_R_INDEX_i 14
#define DAC_R_INDEX__DacRIndex 1


// DAC_W_INDEX
#define DAC_W_INDEX_off_0 0x03c8
#define DAC_W_INDEX_i 15
#define DAC_W_INDEX__DacWIndex 1


// SEQ16
#define SEQ16_off_0 0x03c4
#define SEQ16_i 16
#define SEQ16__SeqIdx 1
#define SEQ16__SeqData 2


// CRTC16B
#define CRTC16B_off_0 0x03b4
#define CRTC16B_i 17
#define CRTC16B__VcrtcIdxB 1
#define CRTC16B__VcrtcDataB 2


// CRTC16D
#define CRTC16D_off_0 0x03d4
#define CRTC16D_i 18
#define CRTC16D__VcrtcIdxD 1
#define CRTC16D__VcrtcDataD 2


// ATTRX
#define ATTRX_off_0 0x03c0
#define ATTRX_i 19
#define ATTRX__AttrIdx 1
#define ATTRX__AttrPalrwEnb 2


// ATTRDW
#define ATTRDW_off_0 0x03c0
#define ATTRDW_i 20
#define ATTRDW__AttrData 1


// ATTRDR
#define ATTRDR_off_0 0x03c1
#define ATTRDR_i 21
#define ATTRDR__AttrData 1


// GRA16
#define GRA16_off_0 0x03ce
#define GRA16_i 22
#define GRA16__GrphIdx 1
#define GRA16__GrphData 2


// ioCRTC_H_TOTAL_DISP
#define ioCRTC_H_TOTAL_DISP_off_0 0x0000
#define ioCRTC_H_TOTAL_DISP_i 23
#define ioCRTC_H_TOTAL_DISP__CrtcHTotal 1
#define ioCRTC_H_TOTAL_DISP__CrtcHDisp 2


// ioCRTC_H_SYNC_STRT_WID
#define ioCRTC_H_SYNC_STRT_WID_off_0 0x0004
#define ioCRTC_H_SYNC_STRT_WID_i 24
#define ioCRTC_H_SYNC_STRT_WID__CrtcHSyncStrt 1
#define ioCRTC_H_SYNC_STRT_WID__CrtcHSyncDly 2
#define ioCRTC_H_SYNC_STRT_WID__CrtcHSyncStrtHi 3
#define ioCRTC_H_SYNC_STRT_WID__CrtcHSyncWid 4
#define ioCRTC_H_SYNC_STRT_WID__CrtcHSyncPol 5


// ioCRTC_V_TOTAL_DISP
#define ioCRTC_V_TOTAL_DISP_off_0 0x0008
#define ioCRTC_V_TOTAL_DISP_i 25
#define ioCRTC_V_TOTAL_DISP__CrtcVTotal 1
#define ioCRTC_V_TOTAL_DISP__CrtcVDisp 2


// ioCRTC_V_SYNC_STRT_WID
#define ioCRTC_V_SYNC_STRT_WID_off_0 0x000c
#define ioCRTC_V_SYNC_STRT_WID_i 26
#define ioCRTC_V_SYNC_STRT_WID__CrtcVSyncStrt 1
#define ioCRTC_V_SYNC_STRT_WID__CrtcVSyncWid 2
#define ioCRTC_V_SYNC_STRT_WID__CrtcVSyncPol 3


// ioCRTC_VLINE_CRNT_VLINE
#define ioCRTC_VLINE_CRNT_VLINE_off_0 0x0010
#define ioCRTC_VLINE_CRNT_VLINE_i 27
#define ioCRTC_VLINE_CRNT_VLINE__CrtcVline 1
#define ioCRTC_VLINE_CRNT_VLINE__CrtcCrntVline 2


// ioCRTC_OFF_PITCH
#define ioCRTC_OFF_PITCH_off_0 0x0014
#define ioCRTC_OFF_PITCH_i 28