ar_dc.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 2,451 行 · 第 1/5 页

#define ioCRTC_OFF_PITCH__CrtcOffset 1
#define ioCRTC_OFF_PITCH__CrtcPitch 2


// ioCRTC_INT_CNTL
#define ioCRTC_INT_CNTL_off_0 0x0018
#define ioCRTC_INT_CNTL_i 29
#define ioCRTC_INT_CNTL__CrtcVblank 1
#define ioCRTC_INT_CNTL__CrtcVblankIntEn 2
#define ioCRTC_INT_CNTL__CrtcVblankIntAk 3
#define ioCRTC_INT_CNTL__CrtcVlineIntEn 4
#define ioCRTC_INT_CNTL__CrtcVlineIntAk 5
#define ioCRTC_INT_CNTL__CrtcVlineSync 6
#define ioCRTC_INT_CNTL__CrtcFrame 7
#define ioCRTC_INT_CNTL__SnapShotEn 8
#define ioCRTC_INT_CNTL__SnapShotIntAk 9
#define ioCRTC_INT_CNTL__I2CIntEn 10
#define ioCRTC_INT_CNTL__I2CIntIntAk 11
#define ioCRTC_INT_CNTL__CapBuf0IntEn 12
#define ioCRTC_INT_CNTL__CapBuf0Int_Ak 13
#define ioCRTC_INT_CNTL__CapBuf1IntEn 14
#define ioCRTC_INT_CNTL__CapBuf1Int_Ak 15
#define ioCRTC_INT_CNTL__OverlayEOFIntEn 16
#define ioCRTC_INT_CNTL__OverlayEOFInt_Ak 17
#define ioCRTC_INT_CNTL__OneShotCapIntEn 18
#define ioCRTC_INT_CNTL__OneShotCapInt_Ak 19
#define ioCRTC_INT_CNTL__BusMasterEolIntEn 20
#define ioCRTC_INT_CNTL__BusMasterEolInt_Ak 21
#define ioCRTC_INT_CNTL__GpInt 22
#define ioCRTC_INT_CNTL__GpIntAk 23
#define ioCRTC_INT_CNTL__VBlankBit2 24


// ioCRTC_GEN_CNTL
#define ioCRTC_GEN_CNTL_off_0 0x001c
#define ioCRTC_GEN_CNTL_i 30
#define ioCRTC_GEN_CNTL__CrtcDblScanEn 1
#define ioCRTC_GEN_CNTL__CrtcInterlaceEn 2
#define ioCRTC_GEN_CNTL__CrtcHSyncDis 3
#define ioCRTC_GEN_CNTL__CrtcVSyncDis 4
#define ioCRTC_GEN_CNTL__CrtcCSyncEn 5
#define ioCRTC_GEN_CNTL__CRTCDisplayDis 6
#define ioCRTC_GEN_CNTL__CrtcVgaXoverscan 7
#define ioCRTC_GEN_CNTL__CrtcPixWidth 8
#define ioCRTC_GEN_CNTL__CrtcBytePixOrder 9
#define ioCRTC_GEN_CNTL__AutoSnapShotTaken 10
#define ioCRTC_GEN_CNTL__ManuSnapShotNow 11
#define ioCRTC_GEN_CNTL__VGA128kApPaging 12
#define ioCRTC_GEN_CNTL__VfcSyncTristate 13
#define ioCRTC_GEN_CNTL__CrtcLockRegs 14
#define ioCRTC_GEN_CNTL__CrtcSyncTristate 15
#define ioCRTC_GEN_CNTL__CrtcExtDispEn 16
#define ioCRTC_GEN_CNTL__CRTCEnable 17
#define ioCRTC_GEN_CNTL__CrtcDispReqEnb 18
#define ioCRTC_GEN_CNTL__VgaAtiLinear 19
#define ioCRTC_GEN_CNTL__CrtcVSyncFallEdge 20
#define ioCRTC_GEN_CNTL__VgaText132 21
#define ioCRTC_GEN_CNTL__VgaXcrtCntEn 22
#define ioCRTC_GEN_CNTL__VgaCurBTest 23


// ioOVR_CLR
#define ioOVR_CLR_off_0 0x0040
#define ioOVR_CLR_i 31
#define ioOVR_CLR__OvrClr8 1
#define ioOVR_CLR__OvrClrB 2
#define ioOVR_CLR__OvrClrG 3
#define ioOVR_CLR__OvrClrR 4


// ioOVR_WID_LEFT_RIGHT
#define ioOVR_WID_LEFT_RIGHT_off_0 0x0044
#define ioOVR_WID_LEFT_RIGHT_i 32
#define ioOVR_WID_LEFT_RIGHT__OvrWidLeft 1
#define ioOVR_WID_LEFT_RIGHT__OvrWidRight 2


// ioOVR_WID_TOP_BOTTOM
#define ioOVR_WID_TOP_BOTTOM_off_0 0x0048
#define ioOVR_WID_TOP_BOTTOM_i 33
#define ioOVR_WID_TOP_BOTTOM__OvrWidTop 1
#define ioOVR_WID_TOP_BOTTOM__OvrWidBottom 2


// ioCUR_CLR0
#define ioCUR_CLR0_off_0 0x0060
#define ioCUR_CLR0_i 34
#define ioCUR_CLR0__CurClr0_8 1
#define ioCUR_CLR0__CurClr0_B 2
#define ioCUR_CLR0__CurClr0_G 3
#define ioCUR_CLR0__CurClr0_R 4


// ioCUR_CLR1
#define ioCUR_CLR1_off_0 0x0064
#define ioCUR_CLR1_i 35
#define ioCUR_CLR1__CurClr1_8 1
#define ioCUR_CLR1__CurClr1_B 2
#define ioCUR_CLR1__CurClr1_G 3
#define ioCUR_CLR1__CurClr1_R 4


// ioCUR_OFFSET
#define ioCUR_OFFSET_off_0 0x0068
#define ioCUR_OFFSET_i 36
#define ioCUR_OFFSET__CurOffset 1


// ioCUR_HORZ_VERT_POSN
#define ioCUR_HORZ_VERT_POSN_off_0 0x006c
#define ioCUR_HORZ_VERT_POSN_i 37
#define ioCUR_HORZ_VERT_POSN__CurHorzPosn 1
#define ioCUR_HORZ_VERT_POSN__CurVertPosn 2


// ioCUR_HORZ_VERT_OFF
#define ioCUR_HORZ_VERT_OFF_off_0 0x0070
#define ioCUR_HORZ_VERT_OFF_i 38
#define ioCUR_HORZ_VERT_OFF__CurHorzOff 1
#define ioCUR_HORZ_VERT_OFF__CurVertOff 2


// ioSCRATCH_REG0
#define ioSCRATCH_REG0_off_0 0x0080
#define ioSCRATCH_REG0_i 39
#define ioSCRATCH_REG0__ScratchReg0 1


// ioSCRATCH_REG1
#define ioSCRATCH_REG1_off_0 0x0084
#define ioSCRATCH_REG1_i 40
#define ioSCRATCH_REG1__ScratchReg1 1


// ioCLOCK_CNTL
#define ioCLOCK_CNTL_off_0 0x0090
#define ioCLOCK_CNTL_i 41
#define ioCLOCK_CNTL__ClockSel 1
#define ioCLOCK_CNTL__PllWrEn 2
#define ioCLOCK_CNTL__PllAddr 3
#define ioCLOCK_CNTL__PllData 4


// ioBUS_CNTL
#define ioBUS_CNTL_off_0 0x00a0
#define ioBUS_CNTL_i 42
#define ioBUS_CNTL__BusDblResync 1
#define ioBUS_CNTL__BusMstrReset 2
#define ioBUS_CNTL__BusFlushBuf 3
#define ioBUS_CNTL__BusStopReqDis 4
#define ioBUS_CNTL__BusAperRegDis 5
#define ioBUS_CNTL__BusExtraPipeDis 6
#define ioBUS_CNTL__BusMasterDis 7
#define ioBUS_CNTL__BIOSRomWrtEn 8
#define ioBUS_CNTL__BusRomDis 9
#define ioBUS_CNTL__PciReadRetryEn 10
#define ioBUS_CNTL__BusDacSnoopEn 11
#define ioBUS_CNTL__BusPciWrtRetryEn 12
#define ioBUS_CNTL__BusWriteWs 13
#define ioBUS_CNTL__BusMstrRdMult 14
#define ioBUS_CNTL__BusMstrRdLine 15
#define ioBUS_CNTL__BusHostErrIntEn 16
#define ioBUS_CNTL__BusHostErrIntAck 17
#define ioBUS_CNTL__BusRdDiscardEn 18
#define ioBUS_CNTL__BusRdAbortEn 19
#define ioBUS_CNTL__BusMstrWs 20
#define ioBUS_CNTL__BusExtRegEn 21
#define ioBUS_CNTL__BusMstrDisconnectEn 22
#define ioBUS_CNTL__BusWriteBurst 23
#define ioBUS_CNTL__BusReadBurst 24
#define ioBUS_CNTL__BusRdyReadDly 25


// ioMEM_CNTL
#define ioMEM_CNTL_off_0 0x00b0
#define ioMEM_CNTL_i 43
#define ioMEM_CNTL__MemSize 1
#define ioMEM_CNTL__MemLatency 2
#define ioMEM_CNTL__MemLatch 3
#define ioMEM_CNTL__MemTrp 4
#define ioMEM_CNTL__MemTrcd 5
#define ioMEM_CNTL__MemTcrd 6
#define ioMEM_CNTL__MemTr2w 7
#define ioMEM_CNTL__MemCasPhase 8
#define ioMEM_CNTL__MemOePullback 9
#define ioMEM_CNTL__MemTras 10
#define ioMEM_CNTL__MemRefreshDis 11
#define ioMEM_CNTL__MemRefreshRate 12
#define ioMEM_CNTL__LowerAperEndian 13
#define ioMEM_CNTL__UpperAperEndian 14
#define ioMEM_CNTL__SharedMemPageSize 15
#define ioMEM_CNTL__SharedMemAdjust 16


// ioMEM_VGA_WP_SEL
#define ioMEM_VGA_WP_SEL_off_0 0x00b4
#define ioMEM_VGA_WP_SEL_i 44
#define ioMEM_VGA_WP_SEL__MemVgaWps0 1
#define ioMEM_VGA_WP_SEL__MemVgaWps1 2


// ioMEM_VGA_RP_SEL
#define ioMEM_VGA_RP_SEL_off_0 0x00b8
#define ioMEM_VGA_RP_SEL_i 45
#define ioMEM_VGA_RP_SEL__MemVgaRps0 1
#define ioMEM_VGA_RP_SEL__MemVgaRps1 2


// ioDAC_REGS
#define ioDAC_REGS_off_0 0x00c0
#define ioDAC_REGS_i 46
#define ioDAC_REGS__DacWIndex 1
#define ioDAC_REGS__DacData 2
#define ioDAC_REGS__DacMask 3
#define ioDAC_REGS__DacRIndex 4


// ioDAC_CNTL
#define ioDAC_CNTL_off_0 0x00c4
#define ioDAC_CNTL_i 47
#define ioDAC_CNTL__DacRangeCntl 1
#define ioDAC_CNTL__DacBlanking 2
#define ioDAC_CNTL__DacCmpDisable 3
#define ioDAC_CNTL__DacCmpOutput 4
#define ioDAC_CNTL__Dac8BitEn 5
#define ioDAC_CNTL__DacDirect 6
#define ioDAC_CNTL__DacPalClkSel 7
#define ioDAC_CNTL__DacVgaAddrEn 8
#define ioDAC_CNTL__DacFeaConEn 9
#define ioDAC_CNTL__DacPdwn 10
#define ioDAC_CNTL__DacType 11
#define ioDAC_CNTL__DacRwWs 12


// ioEXT_DAC_REGS
#define ioEXT_DAC_REGS_off_0 0x00c8
#define ioEXT_DAC_REGS_i 48
#define ioEXT_DAC_REGS__RegSelect 1
#define ioEXT_DAC_REGS__ExtDacData 2
#define ioEXT_DAC_REGS__ExtDacEn 3
#define ioEXT_DAC_REGS__ExtDacWid 4


// ioGEN_TEST_CNTL
#define ioGEN_TEST_CNTL_off_0 0x00d0
#define ioGEN_TEST_CNTL_i 49
#define ioGEN_TEST_CNTL__GenCurEnable 1
#define ioGEN_TEST_CNTL__GenGuiResetb 2
#define ioGEN_TEST_CNTL__GenSoftReset 3
#define ioGEN_TEST_CNTL__GenTestVectMode 4
#define ioGEN_TEST_CNTL__GenTestMode 5
#define ioGEN_TEST_CNTL__GenTestCntEn 6
#define ioGEN_TEST_CNTL__GenCRCEn 7
#define ioGEN_TEST_CNTL__DebugMode 8


// ioCUSTOM_MACRO_CNTL
#define ioCUSTOM_MACRO_CNTL_off_0 0x00d4
#define ioCUSTOM_MACRO_CNTL_i 50
#define ioCUSTOM_MACRO_CNTL__CmdFifoExtSense 1
#define ioCUSTOM_MACRO_CNTL__DspFifoExtSense 2
#define ioCUSTOM_MACRO_CNTL__RdBufFifoExtSense 3
#define ioCUSTOM_MACRO_CNTL__WrBufFifoExtSense 4
#define ioCUSTOM_MACRO_CNTL__GwBufFifoExtSense 5
#define ioCUSTOM_MACRO_CNTL__CacheAExtSense 6
#define ioCUSTOM_MACRO_CNTL__CacheBExtSense 7
#define ioCUSTOM_MACRO_CNTL__TagRamExtSense 8
#define ioCUSTOM_MACRO_CNTL__RdRetFifoExtSense 9
#define ioCUSTOM_MACRO_CNTL__MemCasSkew 10
#define ioCUSTOM_MACRO_CNTL__MemCntlDelay 11
#define ioCUSTOM_MACRO_CNTL__MemCs01Delay 12
#define ioCUSTOM_MACRO_CNTL__MemCs23Delay 13
#define ioCUSTOM_MACRO_CNTL__MemDqmDelay 14
#define ioCUSTOM_MACRO_CNTL__MemMdrDelay 15


// ioCONFIG_CNTL
#define ioCONFIG_CNTL_off_0 0x00dc
#define ioCONFIG_CNTL_i 51
#define ioCONFIG_CNTL__CfgMemApSize 1
#define ioCONFIG_CNTL__CfgMemVgaApEn 2
#define ioCONFIG_CNTL__CfgMemApLoc 3
#define ioCONFIG_CNTL__CfgVgaDis 4


// ioCONFIG_CHIP_ID
#define ioCONFIG_CHIP_ID_off_0 0x00e0
#define ioCONFIG_CHIP_ID_i 52
#define ioCONFIG_CHIP_ID__CfgChipType 1
#define ioCONFIG_CHIP_ID__CfgChipClass 2
#define ioCONFIG_CHIP_ID__CfgChipMajor 3
#define ioCONFIG_CHIP_ID__CfgChipFndId 4
#define ioCONFIG_CHIP_ID__CfgChipMinor 5


// ioCONFIG_STAT0
#define ioCONFIG_STAT0_off_0 0x00e4
#define ioCONFIG_STAT0_i 53
#define ioCONFIG_STAT0__CfgMemType 1
#define ioCONFIG_STAT0__Rom128kEn 2
#define ioCONFIG_STAT0__CfgVgaEn 3
#define ioCONFIG_STAT0__CfgClockEn 4
#define ioCONFIG_STAT0__CfgSharedMemEn 5
#define ioCONFIG_STAT0__VfcSense 6
#define ioCONFIG_STAT0__BoardID 7
#define ioCONFIG_STAT0__BusClkSelStrap 8
#define ioCONFIG_STAT0__FullAGPStrap 9


// ioCONFIG_STAT1
#define ioCONFIG_STAT1_off_0 0x0094
#define ioCONFIG_STAT1_i 54
#define ioCONFIG_STAT1__SubSysDevId 1
#define ioCONFIG_STAT1__SubSysVenId 2
#define ioCONFIG_STAT1__DimmType 3


// ioCONFIG_STAT2
#define ioCONFIG_STAT2_off_0 0x0098
#define ioCONFIG_STAT2_i 55
#define ioCONFIG_STAT2__AGPVcoGain 1
#define ioCONFIG_STAT2__BusType 2
#define ioCONFIG_STAT2__X1ClkSkew 3
#define ioCONFIG_STAT2__AGPSkew 4
#define ioCONFIG_STAT2__CSEnb 5
#define ioCONFIG_STAT2__CFGMemType 6
#define ioCONFIG_STAT2__IDDisable 7
#define ioCONFIG_STAT2__ChgID0 8
#define ioCONFIG_STAT2__PreFetchEn 9
#define ioCONFIG_STAT2__PreTestEn 10
#define ioCONFIG_STAT2__ChgID1 11
#define ioCONFIG_STAT2__VFCSense 12
#define ioCONFIG_STAT2__VGADisable 13
#define ioCONFIG_STAT2__EnIntB 14
#define ioCONFIG_STAT2__RomSize 15
#define ioCONFIG_STAT2__IDSel 16


// ioCRC_SIG
#define ioCRC_SIG_off_0 0x00e8
#define ioCRC_SIG_i 56
#define ioCRC_SIG__CRC_SIG 1


// ioTIMER_CONFIG
#define ioTIMER_CONFIG_off_0 0x0028
#define ioTIMER_CONFIG_i 57
#define ioTIMER_CONFIG__VidIntraAccessTimer 1
#define ioTIMER_CONFIG__SclIntraAccessTimer 2
#define ioTIMER_CONFIG__VidTimerMode 3


// ioMEM_BUF_CNTL
#define ioMEM_BUF_CNTL_off_0 0x002c
#define ioMEM_BUF_CNTL_i 58
#define ioMEM_BUF_CNTL__ZWbFlush 1
#define ioMEM_BUF_CNTL__VidWbFlush 2
#define ioMEM_BUF_CNTL__GuiWbFlush 3
#define ioMEM_BUF_CNTL__HstWbFlush 4
#define ioMEM_BUF_CNTL__SclThresh 5
#define ioMEM_BUF_CNTL__InvalidateRbCache 6
#define ioMEM_BUF_CNTL__SclDispThresh 7


// ioMEM_ADDR_CONFIG
#define ioMEM_ADDR_CONFIG_off_0 0x0034
#define ioMEM_ADDR_CONFIG_i 59
#define ioMEM_ADDR_CONFIG__MemRowMapping 1
#define ioMEM_ADDR_CONFIG__MemColMapping 2
#define ioMEM_ADDR_CONFIG__MemGroupSize 3
#define ioMEM_ADDR_CONFIG__MemWBankCntl 4


// ioDSP_CONFIG
#define ioDSP_CONFIG_off_0 0x0020
#define ioDSP_CONFIG_i 60
#define ioDSP_CONFIG__DspXclksPerQw 1
#define ioDSP_CONFIG__DspBurstStart 2
#define ioDSP_CONFIG__DspLoopLatency 3
#define ioDSP_CONFIG__DspPrecision 4


// ioDSP_ON_OFF
#define ioDSP_ON_OFF_off_0 0x0024
#define ioDSP_ON_OFF_i 61
#define ioDSP_ON_OFF__DspOff 1
#define ioDSP_ON_OFF__DspOn 2


// ioCRT_TRAP
#define ioCRT_TRAP_off_0 0x0038
#define ioCRT_TRAP_i 62
#define ioCRT_TRAP__CrtTrapBaseAddr 1
#define ioCRT_TRAP__DacRgbState 2
#define ioCRT_TRAP__CrtTrapEn 3


// ioVGA_DSP_CONFIG
#define ioVGA_DSP_CONFIG_off_0 0x004c
#define ioVGA_DSP_CONFIG_i 63
#define ioVGA_DSP_CONFIG__VgaDspXclksPerQw 1
#define ioVGA_DSP_CONFIG__VgaDspPrecision1 2
#define ioVGA_DSP_CONFIG__VgaDspPrecision2 3


// ioVGA_DSP_ON_OFF
#define ioVGA_DSP_ON_OFF_off_0 0x0050
#define ioVGA_DSP_ON_OFF_i 64
#define ioVGA_DSP_ON_OFF__VgaDspOff 1
#define ioVGA_DSP_ON_OFF__VgaDspOn 2


// ioMPP_CONFIG
#define ioMPP_CONFIG_off_0 0x00ec
#define ioMPP_CONFIG_i 65
#define ioMPP_CONFIG__MppPrescale 1
#define ioMPP_CONFIG__MppNstates 2
#define ioMPP_CONFIG__MppFormat 3
#define ioMPP_CONFIG__MppWaitState 4
#define ioMPP_CONFIG__MppChkrdyEn 5
#define ioMPP_CONFIG__MppInsertWait 6
#define ioMPP_CONFIG__MppTristateAddr 7
#define ioMPP_CONFIG__MppReadEarly 8
#define ioMPP_CONFIG__MppRwMode 9
#define ioMPP_CONFIG__MppIntMask 10
#define ioMPP_CONFIG__MppAutoIncEn 11
#define ioMPP_CONFIG__MppChkreqEn 12
#define ioMPP_CONFIG__MppChkreqMode 13
#define ioMPP_CONFIG__MppBufferSize 14
#define ioMPP_CONFIG__MppBufferMode 15
#define ioMPP_CONFIG__MppRdy 16
#define ioMPP_CONFIG__MppEn 17


// ioMPP_STROBE_SEQ
#define ioMPP_STROBE_SEQ_off_0 0x00f0
#define ioMPP_STROBE_SEQ_i 66
#define ioMPP_STROBE_SEQ__Stb0Seq 1
#define ioMPP_STROBE_SEQ__Stb1Seq 2


// ioMPP_ADDR
#define ioMPP_ADDR_off_0 0x00f4
#define ioMPP_ADDR_i 67
#define ioMPP_ADDR__MppAddr 1


// ioMPP_DATA
#define ioMPP_DATA_off_0 0x00f8
#define ioMPP_DATA_i 68
#define ioMPP_DATA__MppData 1


// ioTVO_CNTL
#define ioTVO_CNTL_off_0 0x00fc
#define ioTVO_CNTL_i 69
#define ioTVO_CNTL__TvoHTotPix 1
#define ioTVO_CNTL__TvoPcOvrDis 2
#define ioTVO_CNTL__TvoHTotEdge 3
#define ioTVO_CNTL__TvoFilt01En 4
#define ioTVO_CNTL__TvoFiltFfEn 5
#define ioTVO_CNTL__VblankOnly 6
#define ioTVO_CNTL__MpegClkSrc 7
#define ioTVO_CNTL__MpegClkEn 8
#define ioTVO_CNTL__TvoMppOverride 9
#define ioTVO_CNTL__TvoEn 10


// ioGP_IO
#define ioGP_IO_off_0 0x0078
#define ioGP_IO_i 70
#define ioGP_IO__GpIo0 1
#define ioGP_IO__GpIo1 2
#define ioGP_IO__GpIo2 3
#define ioGP_IO__GpIo3 4
#define ioGP_IO__GpIo4 5
#define ioGP_IO__GpIo5 6
#define ioGP_IO__GpIo6 7
#define ioGP_IO__GpIo7 8
#define ioGP_IO__GpIo8 9
#define ioGP_IO__GpIo9 10
#define ioGP_IO__GpIoA 11
#define ioGP_IO__GpIoB 12
#define ioGP_IO__GpIoC 13
#define ioGP_IO__GpIoD 14
#define ioGP_IO__GpIoE 15
#define ioGP_IO__GpIoF 16
#define ioGP_IO__GpIoDir0 17
#define ioGP_IO__GpIoDir1 18
#define ioGP_IO__GpIoDir2 19
#define ioGP_IO__GpIoDir3 20