ar_dc.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 2,451 行 · 第 1/5 页

#define ioGP_IO__GpIoDir4 21
#define ioGP_IO__GpIoDir5 22
#define ioGP_IO__GpIoDir6 23
#define ioGP_IO__GpIoDir7 24
#define ioGP_IO__GpIoDir8 25
#define ioGP_IO__GpIoDir9 26
#define ioGP_IO__GpIoDirA 27
#define ioGP_IO__GpIoDirB 28
#define ioGP_IO__GpIoDirC 29
#define ioGP_IO__GpIoDirD 30
#define ioGP_IO__GpIoDirE 31
#define ioGP_IO__GpIoDirF 32


// ioHW_DEBUG
#define ioHW_DEBUG_off_0 0x007c
#define ioHW_DEBUG_i 71
#define ioHW_DEBUG__HwDebug 1


// **** Memory-mapped:  Register Definitions ****

// CRTC_H_TOTAL_DISP
#define CRTC_H_TOTAL_DISP_off_0 0x0400
#define CRTC_H_TOTAL_DISP_off_1 0x0400
#define CRTC_H_TOTAL_DISP_off_2 0x0400
#define CRTC_H_TOTAL_DISP_i 1
#define CRTC_H_TOTAL_DISP__CrtcHTotal 1
#define CRTC_H_TOTAL_DISP__CrtcHDisp 2


// CRTC_H_SYNC_STRT_WID
#define CRTC_H_SYNC_STRT_WID_off_0 0x0404
#define CRTC_H_SYNC_STRT_WID_off_1 0x0404
#define CRTC_H_SYNC_STRT_WID_off_2 0x0404
#define CRTC_H_SYNC_STRT_WID_i 2
#define CRTC_H_SYNC_STRT_WID__CrtcHSyncStrt 1
#define CRTC_H_SYNC_STRT_WID__CrtcHSyncDly 2
#define CRTC_H_SYNC_STRT_WID__CrtcHSyncStrtHi 3
#define CRTC_H_SYNC_STRT_WID__CrtcHSyncWid 4
#define CRTC_H_SYNC_STRT_WID__CrtcHSyncPol 5


// CRTC_V_TOTAL_DISP
#define CRTC_V_TOTAL_DISP_off_0 0x0408
#define CRTC_V_TOTAL_DISP_off_1 0x0408
#define CRTC_V_TOTAL_DISP_off_2 0x0408
#define CRTC_V_TOTAL_DISP_i 3
#define CRTC_V_TOTAL_DISP__CrtcVTotal 1
#define CRTC_V_TOTAL_DISP__CrtcVDisp 2


// CRTC_V_SYNC_STRT_WID
#define CRTC_V_SYNC_STRT_WID_off_0 0x040c
#define CRTC_V_SYNC_STRT_WID_off_1 0x040c
#define CRTC_V_SYNC_STRT_WID_off_2 0x040c
#define CRTC_V_SYNC_STRT_WID_i 4
#define CRTC_V_SYNC_STRT_WID__CrtcVSyncStrt 1
#define CRTC_V_SYNC_STRT_WID__CrtcVSyncWid 2
#define CRTC_V_SYNC_STRT_WID__CrtcVSyncPol 3


// CRTC_VLINE_CRNT_VLINE
#define CRTC_VLINE_CRNT_VLINE_off_0 0x0410
#define CRTC_VLINE_CRNT_VLINE_off_1 0x0410
#define CRTC_VLINE_CRNT_VLINE_off_2 0x0410
#define CRTC_VLINE_CRNT_VLINE_i 5
#define CRTC_VLINE_CRNT_VLINE__CrtcVline 1
#define CRTC_VLINE_CRNT_VLINE__CrtcCrntVline 2


// CRTC_OFF_PITCH
#define CRTC_OFF_PITCH_off_0 0x0414
#define CRTC_OFF_PITCH_off_1 0x0414
#define CRTC_OFF_PITCH_off_2 0x0414
#define CRTC_OFF_PITCH_i 6
#define CRTC_OFF_PITCH__CrtcOffset 1
#define CRTC_OFF_PITCH__CrtcPitch 2


// CRTC_INT_CNTL
#define CRTC_INT_CNTL_off_0 0x0418
#define CRTC_INT_CNTL_off_1 0x0418
#define CRTC_INT_CNTL_off_2 0x0418
#define CRTC_INT_CNTL_i 7
#define CRTC_INT_CNTL__CrtcVblank 1
#define CRTC_INT_CNTL__CrtcVblankIntEn 2
#define CRTC_INT_CNTL__CrtcVblankIntAk 3
#define CRTC_INT_CNTL__CrtcVlineIntEn 4
#define CRTC_INT_CNTL__CrtcVlineIntAk 5
#define CRTC_INT_CNTL__CrtcVlineSync 6
#define CRTC_INT_CNTL__CrtcFrame 7
#define CRTC_INT_CNTL__SnapShotEn 8
#define CRTC_INT_CNTL__SnapShotIntAk 9
#define CRTC_INT_CNTL__I2CIntEn 10
#define CRTC_INT_CNTL__I2CIntIntAk 11
#define CRTC_INT_CNTL__CapBuf0IntEn 12
#define CRTC_INT_CNTL__CapBuf0Int_Ak 13
#define CRTC_INT_CNTL__CapBuf1IntEn 14
#define CRTC_INT_CNTL__CapBuf1Int_Ak 15
#define CRTC_INT_CNTL__OverlayEOFIntEn 16
#define CRTC_INT_CNTL__OverlayEOFInt_Ak 17
#define CRTC_INT_CNTL__OneShotCapIntEn 18
#define CRTC_INT_CNTL__OneShotCapInt_Ak 19
#define CRTC_INT_CNTL__BusMasterEolIntEn 20
#define CRTC_INT_CNTL__BusMasterEolInt_Ak 21
#define CRTC_INT_CNTL__GpInt 22
#define CRTC_INT_CNTL__GpIntAk 23
#define CRTC_INT_CNTL__VBlankBit2 24


// CRTC_GEN_CNTL
#define CRTC_GEN_CNTL_off_0 0x041c
#define CRTC_GEN_CNTL_off_1 0x041c
#define CRTC_GEN_CNTL_off_2 0x041c
#define CRTC_GEN_CNTL_i 8
#define CRTC_GEN_CNTL__CrtcDblScanEn 1
#define CRTC_GEN_CNTL__CrtcInterlaceEn 2
#define CRTC_GEN_CNTL__CrtcHSyncDis 3
#define CRTC_GEN_CNTL__CrtcVSyncDis 4
#define CRTC_GEN_CNTL__CrtcCSyncEn 5
#define CRTC_GEN_CNTL__CRTCDisplayDis 6
#define CRTC_GEN_CNTL__CrtcVgaXoverscan 7
#define CRTC_GEN_CNTL__CrtcPixWidth 8
#define CRTC_GEN_CNTL__CrtcBytePixOrder 9
#define CRTC_GEN_CNTL__AutoSnapShotTaken 10
#define CRTC_GEN_CNTL__ManuSnapShotNow 11
#define CRTC_GEN_CNTL__VGA128kApPaging 12
#define CRTC_GEN_CNTL__VfcSyncTristate 13
#define CRTC_GEN_CNTL__CrtcLockRegs 14
#define CRTC_GEN_CNTL__CrtcSyncTristate 15
#define CRTC_GEN_CNTL__CrtcExtDispEn 16
#define CRTC_GEN_CNTL__CRTCEnable 17
#define CRTC_GEN_CNTL__CrtcDispReqEnb 18
#define CRTC_GEN_CNTL__VgaAtiLinear 19
#define CRTC_GEN_CNTL__CrtcVSyncFallEdge 20
#define CRTC_GEN_CNTL__VgaText132 21
#define CRTC_GEN_CNTL__VgaXcrtCntEn 22
#define CRTC_GEN_CNTL__VgaCurBTest 23


// OVR_CLR
#define OVR_CLR_off_0 0x0440
#define OVR_CLR_off_1 0x0440
#define OVR_CLR_off_2 0x0440
#define OVR_CLR_i 9
#define OVR_CLR__OvrClr8 1
#define OVR_CLR__OvrClrB 2
#define OVR_CLR__OvrClrG 3
#define OVR_CLR__OvrClrR 4


// OVR_WID_LEFT_RIGHT
#define OVR_WID_LEFT_RIGHT_off_0 0x0444
#define OVR_WID_LEFT_RIGHT_off_1 0x0444
#define OVR_WID_LEFT_RIGHT_off_2 0x0444
#define OVR_WID_LEFT_RIGHT_i 10
#define OVR_WID_LEFT_RIGHT__OvrWidLeft 1
#define OVR_WID_LEFT_RIGHT__OvrWidRight 2


// OVR_WID_TOP_BOTTOM
#define OVR_WID_TOP_BOTTOM_off_0 0x0448
#define OVR_WID_TOP_BOTTOM_off_1 0x0448
#define OVR_WID_TOP_BOTTOM_off_2 0x0448
#define OVR_WID_TOP_BOTTOM_i 11
#define OVR_WID_TOP_BOTTOM__OvrWidTop 1
#define OVR_WID_TOP_BOTTOM__OvrWidBottom 2


// CUR_CLR0
#define CUR_CLR0_off_0 0x0460
#define CUR_CLR0_off_1 0x0460
#define CUR_CLR0_off_2 0x0460
#define CUR_CLR0_i 12
#define CUR_CLR0__CurClr0_8 1
#define CUR_CLR0__CurClr0_B 2
#define CUR_CLR0__CurClr0_G 3
#define CUR_CLR0__CurClr0_R 4


// CUR_CLR1
#define CUR_CLR1_off_0 0x0464
#define CUR_CLR1_off_1 0x0464
#define CUR_CLR1_off_2 0x0464
#define CUR_CLR1_i 13
#define CUR_CLR1__CurClr1_8 1
#define CUR_CLR1__CurClr1_B 2
#define CUR_CLR1__CurClr1_G 3
#define CUR_CLR1__CurClr1_R 4


// CUR_OFFSET
#define CUR_OFFSET_off_0 0x0468
#define CUR_OFFSET_off_1 0x0468
#define CUR_OFFSET_off_2 0x0468
#define CUR_OFFSET_i 14
#define CUR_OFFSET__CurOffset 1


// CUR_HORZ_VERT_POSN
#define CUR_HORZ_VERT_POSN_off_0 0x046c
#define CUR_HORZ_VERT_POSN_off_1 0x046c
#define CUR_HORZ_VERT_POSN_off_2 0x046c
#define CUR_HORZ_VERT_POSN_i 15
#define CUR_HORZ_VERT_POSN__CurHorzPosn 1
#define CUR_HORZ_VERT_POSN__CurVertPosn 2


// CUR_HORZ_VERT_OFF
#define CUR_HORZ_VERT_OFF_off_0 0x0470
#define CUR_HORZ_VERT_OFF_off_1 0x0470
#define CUR_HORZ_VERT_OFF_off_2 0x0470
#define CUR_HORZ_VERT_OFF_i 16
#define CUR_HORZ_VERT_OFF__CurHorzOff 1
#define CUR_HORZ_VERT_OFF__CurVertOff 2


// SCRATCH_REG0
#define SCRATCH_REG0_off_0 0x0480
#define SCRATCH_REG0_off_1 0x0480
#define SCRATCH_REG0_off_2 0x0480
#define SCRATCH_REG0_i 17
#define SCRATCH_REG0__ScratchReg0 1


// SCRATCH_REG1
#define SCRATCH_REG1_off_0 0x0484
#define SCRATCH_REG1_off_1 0x0484
#define SCRATCH_REG1_off_2 0x0484
#define SCRATCH_REG1_i 18
#define SCRATCH_REG1__ScratchReg1 1


// CLOCK_CNTL
#define CLOCK_CNTL_off_0 0x0490
#define CLOCK_CNTL_off_1 0x0490
#define CLOCK_CNTL_off_2 0x0490
#define CLOCK_CNTL_i 19
#define CLOCK_CNTL__ClockSel 1
#define CLOCK_CNTL__PllWrEn 2
#define CLOCK_CNTL__PllAddr 3
#define CLOCK_CNTL__PllData 4


// BUS_CNTL
#define BUS_CNTL_off_0 0x04a0
#define BUS_CNTL_off_1 0x04a0
#define BUS_CNTL_off_2 0x04a0
#define BUS_CNTL_i 20
#define BUS_CNTL__BusDblResync 1
#define BUS_CNTL__BusMstrReset 2
#define BUS_CNTL__BusFlushBuf 3
#define BUS_CNTL__BusStopReqDis 4
#define BUS_CNTL__BusAperRegDis 5
#define BUS_CNTL__BusExtraPipeDis 6
#define BUS_CNTL__BusMasterDis 7
#define BUS_CNTL__BIOSRomWrtEn 8
#define BUS_CNTL__BusRomDis 9
#define BUS_CNTL__PciReadRetryEn 10
#define BUS_CNTL__BusDacSnoopEn 11
#define BUS_CNTL__BusPciWrtRetryEn 12
#define BUS_CNTL__BusWriteWs 13
#define BUS_CNTL__BusMstrRdMult 14
#define BUS_CNTL__BusMstrRdLine 15
#define BUS_CNTL__BusHostErrIntEn 16
#define BUS_CNTL__BusHostErrIntAck 17
#define BUS_CNTL__BusRdDiscardEn 18
#define BUS_CNTL__BusRdAbortEn 19
#define BUS_CNTL__BusMstrWs 20
#define BUS_CNTL__BusExtRegEn 21
#define BUS_CNTL__BusMstrDisconnectEn 22
#define BUS_CNTL__BusWriteBurst 23
#define BUS_CNTL__BusReadBurst 24
#define BUS_CNTL__BusRdyReadDly 25


// BUS_AUX_CNTL
#define BUS_AUX_CNTL_off_0 0x04a4
#define BUS_AUX_CNTL_off_1 0x04a4
#define BUS_AUX_CNTL_off_2 0x04a4
#define BUS_AUX_CNTL_i 21
#define BUS_AUX_CNTL__BusHWmark 1
#define BUS_AUX_CNTL__BusFifoWmarkIntEn 2
#define BUS_AUX_CNTL__BusFifoWmarkIntbusFifoWmarkAK 3


// EXT_MEM_CNTL
#define EXT_MEM_CNTL_off_0 0x04ac
#define EXT_MEM_CNTL_off_1 0x04ac
#define EXT_MEM_CNTL_off_2 0x04ac
#define EXT_MEM_CNTL_i 22
#define EXT_MEM_CNTL__MemCs 1
#define EXT_MEM_CNTL__MemSdramReset 2
#define EXT_MEM_CNTL__MemCycTest 3
#define EXT_MEM_CNTL__MemTileSelect 4
#define EXT_MEM_CNTL__MemClkSelect 5
#define EXT_MEM_CNTL__MemCasLatency 6
#define EXT_MEM_CNTL__MemTileBoundary 7
#define EXT_MEM_CNTL__MemMdaDrive 8
#define EXT_MEM_CNTL__MemMdbDrive 9
#define EXT_MEM_CNTL__MemMdeDelay 10
#define EXT_MEM_CNTL__MemMdoDelay 11
#define EXT_MEM_CNTL__MemMaDrive 12
#define EXT_MEM_CNTL__MemMaDelay 13
#define EXT_MEM_CNTL__MemGcmrs 14
#define EXT_MEM_CNTL__MemCsStrap 15
#define EXT_MEM_CNTL__SdramMemCfg 16
#define EXT_MEM_CNTL__MemAllPageDis 17
#define EXT_MEM_CNTL__MemGroupFaultEn 18


// MEM_CNTL
#define MEM_CNTL_off_0 0x04b0
#define MEM_CNTL_off_1 0x04b0
#define MEM_CNTL_off_2 0x04b0
#define MEM_CNTL_i 23
#define MEM_CNTL__MemSize 1
#define MEM_CNTL__MemLatency 2
#define MEM_CNTL__MemLatch 3
#define MEM_CNTL__MemTrp 4
#define MEM_CNTL__MemTrcd 5
#define MEM_CNTL__MemTcrd 6
#define MEM_CNTL__MemTr2w 7
#define MEM_CNTL__MemCasPhase 8
#define MEM_CNTL__MemOePullback 9
#define MEM_CNTL__MemTras 10
#define MEM_CNTL__MemRefreshDis 11
#define MEM_CNTL__MemRefreshRate 12
#define MEM_CNTL__LowerAperEndian 13
#define MEM_CNTL__UpperAperEndian 14
#define MEM_CNTL__SharedMemPageSize 15
#define MEM_CNTL__SharedMemAdjust 16


// MEM_VGA_WP_SEL
#define MEM_VGA_WP_SEL_off_0 0x04b4
#define MEM_VGA_WP_SEL_off_1 0x04b4
#define MEM_VGA_WP_SEL_off_2 0x04b4
#define MEM_VGA_WP_SEL_i 24
#define MEM_VGA_WP_SEL__MemVgaWps0 1
#define MEM_VGA_WP_SEL__MemVgaWps1 2


// MEM_VGA_RP_SEL
#define MEM_VGA_RP_SEL_off_0 0x04b8
#define MEM_VGA_RP_SEL_off_1 0x04b8
#define MEM_VGA_RP_SEL_off_2 0x04b8
#define MEM_VGA_RP_SEL_i 25
#define MEM_VGA_RP_SEL__MemVgaRps0 1
#define MEM_VGA_RP_SEL__MemVgaRps1 2


// DAC_REGS
#define DAC_REGS_off_0 0x04c0
#define DAC_REGS_off_1 0x04c0
#define DAC_REGS_off_2 0x04c0
#define DAC_REGS_i 26
#define DAC_REGS__DacWIndex 1
#define DAC_REGS__DacData 2
#define DAC_REGS__DacMask 3
#define DAC_REGS__DacRIndex 4


// DAC_CNTL
#define DAC_CNTL_off_0 0x04c4
#define DAC_CNTL_off_1 0x04c4
#define DAC_CNTL_off_2 0x04c4
#define DAC_CNTL_i 27
#define DAC_CNTL__DacRangeCntl 1
#define DAC_CNTL__DacBlanking 2
#define DAC_CNTL__DacCmpDisable 3
#define DAC_CNTL__DacCmpOutput 4
#define DAC_CNTL__Dac8BitEn 5
#define DAC_CNTL__DacDirect 6
#define DAC_CNTL__DacPalClkSel 7
#define DAC_CNTL__DacVgaAddrEn 8
#define DAC_CNTL__DacFeaConEn 9
#define DAC_CNTL__DacPdwn 10
#define DAC_CNTL__DacType 11
#define DAC_CNTL__DacRwWs 12


// EXT_DAC_REGS
#define EXT_DAC_REGS_off_0 0x04c8
#define EXT_DAC_REGS_off_1 0x04c8
#define EXT_DAC_REGS_off_2 0x04c8
#define EXT_DAC_REGS_i 28
#define EXT_DAC_REGS__RegSelect 1
#define EXT_DAC_REGS__ExtDacData 2
#define EXT_DAC_REGS__ExtDacEn 3
#define EXT_DAC_REGS__ExtDacWid 4


// GEN_TEST_CNTL
#define GEN_TEST_CNTL_off_0 0x04d0
#define GEN_TEST_CNTL_off_1 0x04d0
#define GEN_TEST_CNTL_off_2 0x04d0
#define GEN_TEST_CNTL_i 29
#define GEN_TEST_CNTL__GenCurEnable 1
#define GEN_TEST_CNTL__GenGuiResetb 2
#define GEN_TEST_CNTL__GenSoftReset 3
#define GEN_TEST_CNTL__GenTestVectMode 4
#define GEN_TEST_CNTL__GenTestMode 5
#define GEN_TEST_CNTL__GenTestCntEn 6
#define GEN_TEST_CNTL__GenCRCEn 7
#define GEN_TEST_CNTL__DebugMode 8


// CUSTOM_MACRO_CNTL
#define CUSTOM_MACRO_CNTL_off_0 0x04d4
#define CUSTOM_MACRO_CNTL_off_1 0x04d4
#define CUSTOM_MACRO_CNTL_off_2 0x04d4
#define CUSTOM_MACRO_CNTL_i 30
#define CUSTOM_MACRO_CNTL__CmdFifoExtSense 1
#define CUSTOM_MACRO_CNTL__DspFifoExtSense 2
#define CUSTOM_MACRO_CNTL__RdBufFifoExtSense 3
#define CUSTOM_MACRO_CNTL__WrBufFifoExtSense 4
#define CUSTOM_MACRO_CNTL__GwBufFifoExtSense 5
#define CUSTOM_MACRO_CNTL__CacheAExtSense 6
#define CUSTOM_MACRO_CNTL__CacheBExtSense 7
#define CUSTOM_MACRO_CNTL__TagRamExtSense 8
#define CUSTOM_MACRO_CNTL__RdRetFifoExtSense 9
#define CUSTOM_MACRO_CNTL__MemCasSkew 10
#define CUSTOM_MACRO_CNTL__MemCntlDelay 11
#define CUSTOM_MACRO_CNTL__MemCs01Delay 12
#define CUSTOM_MACRO_CNTL__MemCs23Delay 13
#define CUSTOM_MACRO_CNTL__MemDqmDelay 14
#define CUSTOM_MACRO_CNTL__MemMdrDelay 15


// CONFIG_CNTL
#define CONFIG_CNTL_off_0 0x04dc
#define CONFIG_CNTL_off_1 0x04dc
#define CONFIG_CNTL_off_2 0x04dc
#define CONFIG_CNTL_i 31
#define CONFIG_CNTL__CfgMemApSize 1
#define CONFIG_CNTL__CfgMemVgaApEn 2
#define CONFIG_CNTL__CfgMemApLoc 3
#define CONFIG_CNTL__CfgVgaDis 4


// CONFIG_CHIP_ID
#define CONFIG_CHIP_ID_off_0 0x04e0
#define CONFIG_CHIP_ID_off_1 0x04e0
#define CONFIG_CHIP_ID_off_2 0x04e0
#define CONFIG_CHIP_ID_i 32
#define CONFIG_CHIP_ID__CfgChipType 1
#define CONFIG_CHIP_ID__CfgChipClass 2
#define CONFIG_CHIP_ID__CfgChipMajor 3
#define CONFIG_CHIP_ID__CfgChipFndId 4
#define CONFIG_CHIP_ID__CfgChipMinor 5


// CONFIG_STAT0
#define CONFIG_STAT0_off_0 0x04e4
#define CONFIG_STAT0_off_1 0x04e4
#define CONFIG_STAT0_off_2 0x04e4
#define CONFIG_STAT0_i 33
#define CONFIG_STAT0__CfgMemType 1
#define CONFIG_STAT0__Rom128kEn 2
#define CONFIG_STAT0__CfgVgaEn 3
#define CONFIG_STAT0__CfgClockEn 4
#define CONFIG_STAT0__CfgSharedMemEn 5
#define CONFIG_STAT0__VfcSense 6
#define CONFIG_STAT0__BoardID 7
#define CONFIG_STAT0__BusClkSelStrap 8
#define CONFIG_STAT0__FullAGPStrap 9


// CONFIG_STAT1
#define CONFIG_STAT1_off_0 0x0494
#define CONFIG_STAT1_off_1 0x0494
#define CONFIG_STAT1_off_2 0x0494
#define CONFIG_STAT1_i 34
#define CONFIG_STAT1__SubSysDevId 1
#define CONFIG_STAT1__SubSysVenId 2
#define CONFIG_STAT1__DimmType 3


// CONFIG_STAT2
#define CONFIG_STAT2_off_0 0x0498
#define CONFIG_STAT2_off_1 0x0498
#define CONFIG_STAT2_off_2 0x0498
#define CONFIG_STAT2_i 35
#define CONFIG_STAT2__AGPVcoGain 1
#define CONFIG_STAT2__BusType 2
#define CONFIG_STAT2__X1ClkSkew 3
#define CONFIG_STAT2__AGPSkew 4
#define CONFIG_STAT2__CSEnb 5
#define CONFIG_STAT2__CFGMemType 6