ndivider.txt

VHDL源代码实现任意个分频,值得推荐学习

任意奇数分频

只须调整程序中的K值即可!供大家参考!
library ieee;
use ieee.std_logic_1164.all;
entity fredeviderk is
generic (k:integer:=9);
port(clock:in std_logic;
     clkut std_logic);
end;
architecture behav of fredeviderk is
signal count:integer range 0 to k;
signal temp1,temp2:std_logic;
constant k1:integer:=(k-1);
constant k2:integer:=(k-1)/2;
begin
process(clock)
begin
if rising_edge(clock)then
if count=k1 then
count<=0;
temp1<=not temp1;
else count<=count+1;
end if;
end if;
if falling_edge(clock)then
if count=k2 then
temp2<=not temp2;
end if;
end if;
end process;
clk<=temp1 xor temp2;
end behav;