📄 s_machine.vhd
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LIBRARY IEEE;
USE ieee.std_logic_1164.all;
ENTITY s_machine IS
PORT(clk,reset :IN STD_LOGIC;
state_input :BUFFER STD_LOGIC;--串行序列输入
serial :IN STD_LOGIC;--选择输入序列
--input :IN STD_LOGIC;
comb_output :OUT STD_LOGIC; --检测结果输出
state_output :OUT STD_LOGIC_VECTOR(0 to 3)
);
END s_machine;
ARCHITECTURE behav OF s_machine IS
TYPE FSM_ST IS (s0,s1,s2,s3,s4,s5,s6,s7);
SIGNAL current_state,next_state:FSM_ST;
--SIGNAL state_input:std_logic;
COMPONENT right
PORT(clkr,wr:IN std_logic;
CO :OUT std_logic
);
END COMPONENT;
BEGIN
REG:PROCESS(reset,clk)
BEGIN
IF (reset = '1') THEN current_state <= s0;
ELSIF (clk = '1' AND clk'EVENT) THEN
current_state <= next_state;
END IF;
END PROCESS;
U1:right PORT MAP(clkr=>clk,wr=>serial,CO=>state_input);
COM:PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN s0=> comb_output<='0';state_output <= "0000";
IF state_input = '0' THEN next_state<=s0;
ELSE next_state<=s1;
END IF;
WHEN s1=> comb_output<='0';state_output <= "0001";
IF state_input = '0' THEN next_state<=s0;
ELSE next_state<=s2;
END IF;
WHEN s2=> comb_output<='0';state_output <= "0010";
IF state_input = '0' THEN next_state<=s0;
ELSE next_state<=s3;
END IF;
WHEN s3=> comb_output<='0';state_output <= "0011";
IF state_input = '1' THEN next_state<=s3;
ELSE next_state<=s4;
END IF;
WHEN s4=> comb_output<='0';state_output <= "0100";
IF state_input = '1' THEN next_state<=s1;
ELSE next_state<=s5;
END IF;
WHEN s5=> comb_output<='0';state_output <= "0101";
IF state_input = '0' THEN next_state<=s0;
ELSE next_state<=s6;
END IF;
WHEN s6=> comb_output<='0';state_output <= "0110";
IF state_input = '1' THEN next_state<=s2;
ELSE next_state<=s7;
END IF;
WHEN s7=> comb_output<='1';state_output <= "0111";
IF state_input = '1' THEN next_state<=s1;
ELSE next_state<=s0;
END IF;
END CASE;
END PROCESS;
END behav;
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