dpll.sim.vwf

DPLL同步提取有一定效果

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 60000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("reset")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("signal_in")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("signal_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("syn")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 6000;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("reset")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 60000.0;
	}
}

TRANSITION_LIST("signal_in")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 8;
			LEVEL 0 FOR 700.0;
			LEVEL 1 FOR 700.0;
		}
		LEVEL 0 FOR 32900.0;
		LEVEL 1 FOR 700.0;
		NODE
		{
			REPEAT = 10;
			LEVEL 0 FOR 700.0;
			LEVEL 1 FOR 700.0;
		}
		LEVEL 0 FOR 700.0;
		LEVEL 1 FOR 500.0;
	}
}

TRANSITION_LIST("signal_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 606.803;
		LEVEL 1 FOR 660.0;
		LEVEL 0 FOR 670.0;
		LEVEL 1 FOR 690.0;
		LEVEL 0 FOR 680.0;
		LEVEL 1 FOR 690.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 700.0;
			LEVEL 1 FOR 700.0;
		}
		LEVEL 0 FOR 700.0;
		NODE
		{
			REPEAT = 22;
			LEVEL 1 FOR 810.0;
			LEVEL 0 FOR 650.0;
		}
		LEVEL 1 FOR 710.0;
		NODE
		{
			REPEAT = 11;
			LEVEL 0 FOR 700.0;
			LEVEL 1 FOR 700.0;
		}
		LEVEL 0 FOR 73.197;
	}
}

TRANSITION_LIST("syn")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "reset";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "signal_in";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "signal_out";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "syn";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 15925;
	MASTER = TRUE;
}
;