cnt10.vhd

用VHDL语言编的带有异步清零功能的十进制计数器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk: in std_logic;
     clrn:in std_logic;
        Q: buffer std_logic_vector(3 downto 0);
      co: out std_logic);
end cnt10;
architecture art of cnt10 is
begin
     process(clk,clrn) is
     begin
          if(clrn='0') then
            Q<="0000";
         elsif(clk'event and clk='1') then
                if(Q<9) then
                    Q<=Q+1;
                else
                    co<='1';
                    Q<="0000";
               end if;
         end if;
    end process;
end art;