control.vhd

来自「电子钏的硬件描述语言设计」· VHDL 代码 · 共 43 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity control is
port
 (
  clk1024,clk500,sa,sb,sc,en: in std_logic;
  q1 : in std_logic_vector(7 downto 0);
  q2 : in std_logic_vector(7 downto 0);
  bee: out std_logic;
  clks: buffer std_logic;
  clrc,setb,seta:out std_logic
 );
end control;

architecture aa of control is
signal count,count500 : integer range 0 to 1023;
begin

PROCESS(clk1024)
BEGIN
IF rising_edge(clk1024) then
 if count>=1023 then count<=0; else count<=count+1; end if;
 if count>=511 then clks<='1'; else clks<='0'; end if;
END IF;
END PROCESS;

PROCESS (clks)
BEGIN
-- @1024Hz(need 1s)
IF RISING_EDGE(clks) THEN
  seta<=sa;
  setb<=sb;
end if;
END PROCESS;

clrc<=sc;
bee<=clk500 when q2(7 downto 0)="01011001" and q1(7 downto 4)="0101" and q1(0)='0' else
	 clk1024 when q2(7 downto 0) & q1(7 downto 0)="0000000000000000" else '0';
end aa;