📄 cpldtest.rpt
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Project Information d:\cpldnew\cpldtest.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 01/05/2006 17:24:05
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cpldtest EPM7128SQC160-15 0 1 0 1 0 0 %
User Pins: 0 1 0
Project Information d:\cpldnew\cpldtest.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'b' is stuck at GND
Warning: Node 'PIN_NAME' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Project Information d:\cpldnew\cpldtest.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
cpldtest@50 b
cpldtest@50 --------- PIN_NAME
Device-Specific Information: d:\cpldnew\cpldtest.rpt
cpldtest
***** Logic for device 'cpldtest' compiled without errors.
Device: EPM7128SQC160-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S V S S S S S S S S S S S S
E E E E E E E E E E E E C E E E E V E E E E E E E E
R R R N N N N R R R R R R R R R C R R R R C R R R R R N N N N R R R
V V V . . . . V V V V V G V V V V I G G G G G V V V V C V V V V V . . . . V V V
E E E C C C C E E E E E N E E E E N N N N N N E E E E I E E E E E C C C C E E E
D D D . . . . D D D D D D D D D D T D D D D D D D D D O D D D D D . . . . D D D
----------------------------------------------------------------------------------_
/ 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 |_
/ 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 |
N.C. | 1 120 | N.C.
N.C. | 2 119 | N.C.
N.C. | 3 118 | N.C.
N.C. | 4 117 | N.C.
N.C. | 5 116 | N.C.
N.C. | 6 115 | N.C.
N.C. | 7 114 | N.C.
VCCIO | 8 113 | GND
#TDI | 9 112 | #TDO
RESERVED | 10 111 | RESERVED
RESERVED | 11 110 | RESERVED
RESERVED | 12 109 | RESERVED
RESERVED | 13 108 | RESERVED
RESERVED | 14 107 | RESERVED
RESERVED | 15 106 | RESERVED
RESERVED | 16 105 | RESERVED
GND | 17 104 | VCCIO
RESERVED | 18 103 | RESERVED
RESERVED | 19 102 | RESERVED
RESERVED | 20 101 | RESERVED
RESERVED | 21 EPM7128SQC160-15 100 | RESERVED
#TMS | 22 99 | #TCK
RESERVED | 23 98 | RESERVED
RESERVED | 24 97 | RESERVED
RESERVED | 25 96 | RESERVED
VCCIO | 26 95 | GND
RESERVED | 27 94 | RESERVED
RESERVED | 28 93 | RESERVED
RESERVED | 29 92 | RESERVED
RESERVED | 30 91 | RESERVED
RESERVED | 31 90 | RESERVED
RESERVED | 32 89 | RESERVED
RESERVED | 33 88 | RESERVED
N.C. | 34 87 | N.C.
N.C. | 35 86 | N.C.
N.C. | 36 85 | N.C.
N.C. | 37 84 | N.C.
N.C. | 38 83 | N.C.
N.C. | 39 82 | N.C.
N.C. | 40 81 | N.C.
| 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 _|
\ 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 |
\-----------------------------------------------------------------------------------
R G R N N N N R R b R R R R V R R R R G V R R R R G R R R R R R R N N N N R V R
E N E . . . . E E E E E E C E E E E N C E E E E N E E E E E E E . . . . E C E
S D S C C C C S S S S S S C S S S S D C S S S S D S S S S S S S C C C C S C S
E E . . . . E E E E E E I E E E E I E E E E E E E E E E E . . . . E I E
R R R R R R R R O R R R R N R R R R R R R R R R R R O R
V V V V V V V V V V V V T V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\cpldnew\cpldtest.rpt
cpldtest
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/12( 8%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 1/12( 8%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 1/16( 6%) 1/12( 8%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 0/16( 0%) 1/12( 8%) 0/16( 0%) 0/36( 0%)
G: LC97 - LC112 0/16( 0%) 1/12( 8%) 0/16( 0%) 0/36( 0%)
H: LC113 - LC128 0/16( 0%) 0/12( 0%) 0/16( 0%) 0/36( 0%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 5/96 ( 5%)
Total logic cells used: 1/128 ( 0%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 1/128 ( 0%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 0.00
Total fan-in: 0
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