📄 cpld4gdf.rpt
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Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 (37) (C) INPUT 0 0 0 0 0 9 3 A0
30 (38) (C) INPUT 0 0 0 0 0 16 4 A1
29 (40) (C) INPUT 0 0 0 0 0 35 5 A2
28 (41) (C) INPUT 0 0 0 0 0 35 5 A3
27 (43) (C) INPUT 0 0 0 0 0 2 0 A12
25 (44) (C) INPUT 0 0 0 0 0 2 0 A13
24 (45) (C) INPUT 0 0 0 0 0 11 1 A14
23 (46) (C) INPUT 0 0 0 0 0 37 5 A15
111 110 G BIDIR 0 0 0 5 1 0 0 BD0
110 109 G BIDIR 0 0 0 5 1 0 0 BD1
109 108 G BIDIR 0 0 0 5 1 0 0 BD2
108 107 G BIDIR 0 0 0 5 1 0 0 BD3
107 105 G BIDIR 0 0 0 5 1 0 0 BD4
106 104 G BIDIR 0 0 0 5 1 0 0 BD5
105 102 G BIDIR 0 0 0 5 1 0 0 BD6
103 101 G BIDIR 0 0 0 5 1 0 0 BD7
50 (60) (D) INPUT 0 0 0 0 0 0 0 CAP1/QEP1/IOPA3
53 (56) (D) INPUT 0 0 0 0 0 1 0 CAP2/QEP2/IOPA4
54 (54) (D) INPUT 0 0 0 0 0 0 0 CAP3/IOPA5
32 (36) (C) INPUT 0 0 0 0 0 0 0 CAP4/QEP3/IOPE7
48 (62) (D) INPUT 0 0 0 0 0 2 0 /DS
21 17 B BIDIR 0 0 0 0 0 3 0 D0
20 19 B BIDIR 0 0 0 0 0 3 0 D1
19 20 B BIDIR 0 0 0 0 0 3 0 D2
16 22 B BIDIR 0 0 0 0 0 3 0 D3
15 24 B BIDIR 0 0 0 1 0 2 0 D4
14 25 B BIDIR 0 0 0 1 0 2 0 D5
13 27 B BIDIR 0 0 0 1 0 2 0 D6
12 28 B BIDIR 0 0 0 1 0 2 0 D7
160 (1) (A) INPUT 0 0 0 0 0 0 0 HOSTRESET
51 (59) (D) INPUT 0 0 0 0 0 37 5 /IOS
57 (52) (D) INPUT 0 0 0 0 0 1 0 K0
58 (51) (D) INPUT 0 0 0 0 0 1 0 K1
59 (49) (D) INPUT 0 0 0 0 0 1 0 K2
62 (65) (E) INPUT 0 0 0 0 0 1 0 K3
63 (67) (E) INPUT 0 0 0 0 0 1 0 K4
64 (68) (E) INPUT 0 0 0 0 0 1 0 K5
65 (69) (E) INPUT 0 0 0 0 0 1 0 K6
67 (70) (E) INPUT 0 0 0 0 0 1 0 K7
49 (61) (D) INPUT 0 0 0 0 0 2 0 /PS
88 (83) (F) INPUT 0 0 0 0 0 0 0 /PWRONRST
41 (33) (C) INPUT 0 0 0 0 0 3 1 /RD
151 8 A BIDIR 0 0 0 1 0 1 0 RD0
150 9 A BIDIR 0 0 0 1 0 1 0 RD1
149 11 A BIDIR 0 0 0 1 0 1 0 RD2
147 12 A BIDIR 0 0 0 1 0 1 0 RD3
146 13 A BIDIR 0 0 0 1 0 1 0 RD4
145 14 A BIDIR 0 0 0 1 0 1 0 RD5
144 16 A BIDIR 0 0 0 1 0 1 0 RD6
137 128 H BIDIR 0 0 0 1 0 1 0 RD7
72 (77) (E) INPUT 0 0 0 0 0 2 0 SD4
73 (78) (E) INPUT 0 0 0 0 0 2 0 SD5
78 (80) (E) INPUT 0 0 0 0 0 2 0 SD6
80 (81) (F) INPUT 0 0 0 0 0 2 0 SD7
33 (35) (C) INPUT 0 0 0 0 0 1 0 /STRB
52 (57) (D) INPUT 0 0 0 0 0 9 0 SWRESET
56 (53) (D) INPUT 0 0 0 0 0 0 0 TEFREST
134 124 H BIDIR 0 0 0 5 1 0 0 UD0
132 123 H BIDIR 0 0 0 5 1 0 0 UD1
131 121 H BIDIR 0 0 0 5 1 0 0 UD2
130 120 H BIDIR 0 0 0 5 1 0 0 UD3
129 118 H BIDIR 0 0 0 5 1 0 0 UD4
128 117 H BIDIR 0 0 0 5 1 0 0 UD5
123 116 H BIDIR 0 0 0 5 1 0 0 UD6
122 115 H BIDIR 0 0 0 5 1 0 0 UD7
43 (64) (D) INPUT 0 0 0 0 0 8 0 /WE
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
111 110 G TRI t 0 0 0 5 1 0 0 BD0
110 109 G TRI t 0 0 0 5 1 0 0 BD1
109 108 G TRI t 0 0 0 5 1 0 0 BD2
108 107 G TRI t 0 0 0 5 1 0 0 BD3
107 105 G TRI t 0 0 0 5 1 0 0 BD4
106 104 G TRI t 0 0 0 5 1 0 0 BD5
105 102 G TRI t 0 0 0 5 1 0 0 BD6
103 101 G TRI t 0 0 0 5 1 0 0 BD7
153 5 A OUTPUT t 0 0 0 7 0 0 0 /BUFFER
101 99 G OUTPUT t 0 0 0 7 0 0 0 /CDR
100 97 G OUTPUT t 0 0 0 7 0 0 0 /CDW
159 3 A FF t 1 0 0 11 0 0 0 CON_INTSW
158 4 A OUTPUT t 0 0 0 4 0 0 0 /DACS
21 17 B TRI t 0 0 0 0 0 3 0 D0
20 19 B TRI t 0 0 0 0 0 3 0 D1
19 20 B TRI t 0 0 0 0 0 3 0 D2
16 22 B TRI t 0 0 0 0 0 3 0 D3
15 24 B TRI t 0 0 0 1 0 2 0 D4
14 25 B TRI t 0 0 0 1 0 2 0 D5
13 27 B TRI t 0 0 0 1 0 2 0 D6
12 28 B TRI t 0 0 0 1 0 2 0 D7
102 100 G OUTPUT t 0 0 0 1 0 0 0 LC/D
98 94 F OUTPUT t 0 0 0 1 0 0 0 /LCE
97 93 F FF t 1 1 0 5 1 0 0 L1 (|74273:69|:19)
96 92 F FF t 1 1 0 5 1 0 0 L2 (|74273:69|:18)
94 91 F FF t 1 1 0 5 1 0 0 L3 (|74273:69|:17)
93 89 F FF t 1 1 0 5 1 0 0 L4 (|74273:69|:16)
92 88 F FF t 1 1 0 5 1 0 0 L5 (|74273:69|:15)
91 86 F FF t 1 1 0 5 1 0 0 L6 (|74273:69|:14)
90 85 F FF t 1 1 0 5 1 0 0 L7 (|74273:69|:13)
89 84 F FF t 1 1 0 5 1 0 0 L8 (|74273:69|:12)
11 29 B OUTPUT t 0 0 0 3 0 0 0 /RAMOE
10 30 B OUTPUT t 0 0 0 3 0 0 0 /RAMWE
151 8 A TRI t 0 0 0 1 0 1 0 RD0
150 9 A TRI t 0 0 0 1 0 1 0 RD1
149 11 A TRI t 0 0 0 1 0 1 0 RD2
147 12 A TRI t 0 0 0 1 0 1 0 RD3
146 13 A TRI t 0 0 0 1 0 1 0 RD4
145 14 A TRI t 0 0 0 1 0 1 0 RD5
144 16 A TRI t 0 0 0 1 0 1 0 RD6
137 128 H TRI t 0 0 0 1 0 1 0 RD7
18 21 B OUTPUT t 0 0 0 1 0 0 0 /RS
71 76 E TRI/FF t 1 1 0 7 1 0 0 SD0
70 75 E TRI/FF t 1 1 0 7 1 0 0 SD1
69 73 E TRI/FF t 1 1 0 7 1 0 0 SD2
68 72 E TRI/FF t 1 1 0 7 1 0 0 SD3
121 113 H OUTPUT t 0 0 0 5 0 0 0 /UCS
134 124 H TRI t 0 0 0 5 1 0 0 UD0
132 123 H TRI t 0 0 0 5 1 0 0 UD1
131 121 H TRI t 0 0 0 5 1 0 0 UD2
130 120 H TRI t 0 0 0 5 1 0 0 UD3
129 118 H TRI t 0 0 0 5 1 0 0 UD4
128 117 H TRI t 0 0 0 5 1 0 0 UD5
123 116 H TRI t 0 0 0 5 1 0 0 UD6
122 115 H TRI t 0 0 0 5 1 0 0 UD7
135 125 H OUTPUT t 0 0 0 6 0 0 0 /UOE
136 126 H OUTPUT t 0 0 0 6 0 0 0 /UWE
152 6 A OUTPUT t 0 0 0 4 0 0 0 /XFER
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(78) 80 E SOFT s t 0 0 0 5 0 0 0 BD5~1
(58) 51 D SOFT s t 0 0 0 7 0 0 0 D6~1
(65) 69 E SOFT s t 0 0 0 6 0 0 0 RD7~1
(33) 35 C SOFT s t 0 0 0 5 0 0 0 UD7~1
(63) 67 E SOFT s t 0 0 0 6 0 0 0 |74374:99|~16~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------------- LC5 /BUFFER
| +------------------- LC3 CON_INTSW
| | +----------------- LC4 /DACS
| | | +--------------- LC8 RD0
| | | | +------------- LC9 RD1
| | | | | +----------- LC11 RD2
| | | | | | +--------- LC12 RD3
| | | | | | | +------- LC13 RD4
| | | | | | | | +----- LC14 RD5
| | | | | | | | | +--- LC16 RD6
| | | | | | | | | | +- LC6 /XFER
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
31 -> * * - - - - - - - - - | * - - * * - * - | <-- A0
30 -> * * - - - - - - - - - | * - - * * - * - | <-- A1
29 -> * * * - - - - - - - * | * - * * * * * * | <-- A2
28 -> * * * - - - - - - - * | * - * * * * * * | <-- A3
23 -> * * * - - - - - - - * | * - * * * * * * | <-- A15
51 -> * * * - - - - - - - * | * - * * * * * * | <-- /IOS
57 -> - - - * - - - - - - - | * - - - - - - - | <-- K0
58 -> - - - - * - - - - - - | * - - - - - - - | <-- K1
59 -> - - - - - * - - - - - | * - - - - - - - | <-- K2
62 -> - - - - - - * - - - - | * - - - - - - - | <-- K3
63 -> - - - - - - - * - - - | * - - - - - - - | <-- K4
64 -> - - - - - - - - * - - | * - - - - - - - | <-- K5
65 -> - - - - - - - - - * - | * - - - - - - - | <-- K6
72 -> - * - - - - - - - - - | * * - - - - - - | <-- SD4
73 -> - * - - - - - - - - - | * * - - - - - - | <-- SD5
78 -> - * - - - - - - - - - | * * - - - - - - | <-- SD6
80 -> - * - - - - - - - - - | * * - - - - - - | <-- SD7
33 -> * - - - - - - - - - - | * - - - - - - - | <-- /STRB
43 -> - * - - - - - - - - - | * * - - * - * * | <-- /WE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------- LC17 D0
| +------------------- LC19 D1
| | +----------------- LC20 D2
| | | +--------------- LC22 D3
| | | | +------------- LC24 D4
| | | | | +----------- LC25 D5
| | | | | | +--------- LC27 D6
| | | | | | | +------- LC28 D7
| | | | | | | | +----- LC29 /RAMOE
| | | | | | | | | +--- LC30 /RAMWE
| | | | | | | | | | +- LC21 /RS
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
48 -> - - - - - - - - * * - | - * - - - - - - | <-- /DS
49 -> - - - - - - - - * * - | - * - - - - - - | <-- /PS
41 -> - - - - - - - - * - - | - * - * - - * * | <-- /RD
72 -> - - - - * - - - - - - | * * - - - - - - | <-- SD4
73 -> - - - - - * - - - - - | * * - - - - - - | <-- SD5
78 -> - - - - - - * - - - - | * * - - - - - - | <-- SD6
80 -> - - - - - - - * - - - | * * - - - - - - | <-- SD7
52 -> - - - - - - - - - - * | - * - - - * - - | <-- SWRESET
43 -> - - - - - - - - - * - | * * - - * - * * | <-- /WE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+- LC35 UD7~1
|
| Other LABs fed by signals
| that feed LAB 'C'
LC | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
29 -> * | * - * * * * * * | <-- A2
28 -> * | * - * * * * * * | <-- A3
24 -> * | - - * - - - - * | <-- A14
23 -> * | * - * * * * * * | <-- A15
51 -> * | * - * * * * * * | <-- /IOS
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpldnew\cpld4gdf.rpt
cpld4gdf
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+- LC51 D6~1
|
| Other LABs fed by signals
| that feed LAB 'D'
LC | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
31 -> * | * - - * * - * - | <-- A0
30 -> * | * - - * * - * - | <-- A1
29 -> * | * - * * * * * * | <-- A2
28 -> * | * - * * * * * * | <-- A3
23 -> * | * - * * * * * * | <-- A15
51 -> * | * - * * * * * * | <-- /IOS
41 -> * | - * - * - - * * | <-- /RD
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
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