u1.rpt

用maxplus2实现的一种通用逻辑模块

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 e:\cpldnew\u1.rpt
u1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                     Logic cells placed in LAB 'B'
        +--------------------------- LC29 CDR
        | +------------------------- LC19 CDW
        | | +----------------------- LC32 DACS
        | | | +--------------------- LC26 INTRSW
        | | | | +------------------- LC28 LCD
        | | | | | +----------------- LC31 LEDS
        | | | | | | +--------------- LC18 RDSW
        | | | | | | | +------------- LC21 SWCE
        | | | | | | | | +----------- LC23 SWITCHES
        | | | | | | | | | +--------- LC24 UCS
        | | | | | | | | | | +------- LC27 UOE
        | | | | | | | | | | | +----- LC22 UWE
        | | | | | | | | | | | | +--- LC17 WRSW
        | | | | | | | | | | | | | +- LC30 XFER
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
9    -> * * - * - - * * * - - - * - | - * | <-- A0
16   -> * * - * * - * * * - - - * - | - * | <-- A1
19   -> * * * * * * * * * * - - * * | - * | <-- A2
20   -> * * * * * * * * * * - - * * | - * | <-- A3
21   -> - - - - - - - - - - * * - - | - * | <-- A12
17   -> - - - - - - - - - - * * - - | - * | <-- A13
18   -> - - - - - - - - - * * * - - | - * | <-- A14
14   -> * * * * * * * * * * * * * * | - * | <-- A15
1    -> * * * * * * * * * * * * * * | - * | <-- IOS
44   -> * - - - - - * - - - * - - - | * * | <-- RD
43   -> - * - * - - - - - - - * * - | * * | <-- WE


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 e:\cpldnew\u1.rpt
u1

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A12      : INPUT;
A13      : INPUT;
A14      : INPUT;
A15      : INPUT;
DS       : INPUT;
IOS      : INPUT;
PS       : INPUT;
RD       : INPUT;
SWRESET  : INPUT;
WE       : INPUT;

-- Node name is 'CDR' 
-- Equation name is 'CDR', location is LC029, type is output.
 CDR     = LCELL( _EQ001 $  VCC);
  _EQ001 =  A0 & !A1 & !A2 &  A3 & !A15 & !IOS & !RD;

-- Node name is 'CDW' 
-- Equation name is 'CDW', location is LC019, type is output.
 CDW     = LCELL( _EQ002 $  VCC);
  _EQ002 =  A0 & !A1 & !A2 &  A3 & !A15 & !IOS & !WE;

-- Node name is 'DACS' 
-- Equation name is 'DACS', location is LC032, type is output.
 DACS    = LCELL( _EQ003 $  VCC);
  _EQ003 = !A2 & !A3 & !A15 & !IOS;

-- Node name is 'INTRSW' 
-- Equation name is 'INTRSW', location is LC026, type is output.
 INTRSW  = LCELL( _EQ004 $  GND);
  _EQ004 = !A0 &  A1 &  A2 & !A3 & !A15 & !IOS & !WE;

-- Node name is 'LCD' 
-- Equation name is 'LCD', location is LC028, type is output.
 LCD     = LCELL( _EQ005 $  GND);
  _EQ005 = !A1 & !A2 &  A3 & !A15 & !IOS;

-- Node name is 'LEDS' 
-- Equation name is 'LEDS', location is LC031, type is output.
 LEDS    = LCELL( _EQ006 $  VCC);
  _EQ006 =  A2 &  A3 & !A15 & !IOS;

-- Node name is 'RAMOE' 
-- Equation name is 'RAMOE', location is LC003, type is output.
 RAMOE   = LCELL( _EQ007 $  RD);
  _EQ007 =  DS &  PS & !RD;

-- Node name is 'RAMWE' 
-- Equation name is 'RAMWE', location is LC002, type is output.
 RAMWE   = LCELL( _EQ008 $  WE);
  _EQ008 =  DS &  PS & !WE;

-- Node name is 'RDSW' 
-- Equation name is 'RDSW', location is LC018, type is output.
 RDSW    = LCELL( _EQ009 $  VCC);
  _EQ009 =  A0 & !A1 &  A2 & !A3 & !A15 & !IOS & !RD;

-- Node name is 'RS' 
-- Equation name is 'RS', location is LC001, type is output.
 RS      = LCELL(!SWRESET $  GND);

-- Node name is 'SWCE' 
-- Equation name is 'SWCE', location is LC021, type is output.
 SWCE    = LCELL( _EQ010 $  VCC);
  _EQ010 =  A0 & !A1 &  A2 & !A3 & !A15 & !IOS;

-- Node name is 'SWITCHES' 
-- Equation name is 'SWITCHES', location is LC023, type is output.
 SWITCHES = LCELL( _EQ011 $  VCC);
  _EQ011 =  A0 &  A1 & !A2 &  A3 & !A15 & !IOS;

-- Node name is 'UCS' 
-- Equation name is 'UCS', location is LC024, type is output.
 UCS     = LCELL( _EQ012 $  GND);
  _EQ012 = !A2 & !A3 & !A14 &  A15 & !IOS;

-- Node name is 'UOE' 
-- Equation name is 'UOE', location is LC027, type is output.
 UOE     = LCELL( _EQ013 $  VCC);
  _EQ013 = !A12 & !A13 & !A14 &  A15 & !IOS & !RD;

-- Node name is 'UWE' 
-- Equation name is 'UWE', location is LC022, type is output.
 UWE     = LCELL( _EQ014 $  VCC);
  _EQ014 = !A12 & !A13 & !A14 &  A15 & !IOS & !WE;

-- Node name is 'WRSW' 
-- Equation name is 'WRSW', location is LC017, type is output.
 WRSW    = LCELL( _EQ015 $  VCC);
  _EQ015 =  A0 & !A1 &  A2 & !A3 & !A15 & !IOS & !WE;

-- Node name is 'XFER' 
-- Equation name is 'XFER', location is LC030, type is output.
 XFER    = LCELL( _EQ016 $  VCC);
  _EQ016 = !A2 &  A3 & !A15 & !IOS;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                          e:\cpldnew\u1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,295K