📄 cpld4gdf00.tan.qmsg
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{ "Info" "ITAN_NO_REG2REG_EXIST" "A15 " "Info: No valid register-to-register data paths exist for clock \"A15\"" { } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A2 " "Info: No valid register-to-register data paths exist for clock \"A2\"" { } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "/IOS " "Info: No valid register-to-register data paths exist for clock \"/IOS\"" { } { } 0}
{ "Info" "ITDB_TSU_RESULT" "74273:69\|12 RD\[7\] /IOS -4.000 ns register " "Info: tsu for register \"74273:69\|12\" (data pin = \"RD\[7\]\", clock pin = \"/IOS\") is -4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RD\[7\] 1 PIN PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_132; Fanout = 1; PIN Node = 'RD\[7\]'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { RD[7] } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 184 1456 1632 200 "RD\[7..0\]" "" } { 176 1376 1456 192 "RD\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns RD~0 2 COMB IO123 1 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO123; Fanout = 1; COMB Node = 'RD~0'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "2.000 ns" { RD[7] RD~0 } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 184 1456 1632 200 "RD\[7..0\]" "" } { 176 1376 1456 192 "RD\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns 74273:69\|12 3 REG LC92 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC92; Fanout = 1; REG Node = '74273:69\|12'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "8.000 ns" { RD~0 74273:69|12 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74273.bdf" { { 888 320 384 968 "12" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "10.000 ns" { RD[7] RD~0 74273:69|12 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { RD[7] RD~0 74273:69|12 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "74273.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74273.bdf" { { 888 320 384 968 "12" "" } } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "/IOS destination 18.000 ns - Shortest register " "Info: - Shortest clock path from clock \"/IOS\" to destination register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns /IOS 1 CLK PIN_21 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 6; CLK Node = '/IOS'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { /IOS } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 104 432 600 120 "/IOS" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns u11:109\|u1:94\|LEDS~29 2 COMB SEXP81 8 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP81; Fanout = 8; COMB Node = 'u11:109\|u1:94\|LEDS~29'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "10.000 ns" { /IOS u11:109|u1:94|LEDS~29 } "NODE_NAME" } "" } } { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns 74273:69\|12 3 REG LC92 1 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC92; Fanout = 1; REG Node = '74273:69\|12'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "6.000 ns" { u11:109|u1:94|LEDS~29 74273:69|12 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74273.bdf" { { 888 320 384 968 "12" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 88.89 % " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 11.11 % " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "18.000 ns" { /IOS u11:109|u1:94|LEDS~29 74273:69|12 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "18.000 ns" { /IOS /IOS~out u11:109|u1:94|LEDS~29 74273:69|12 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "10.000 ns" { RD[7] RD~0 74273:69|12 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { RD[7] RD~0 74273:69|12 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "18.000 ns" { /IOS u11:109|u1:94|LEDS~29 74273:69|12 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "18.000 ns" { /IOS /IOS~out u11:109|u1:94|LEDS~29 74273:69|12 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "/IOS LC/D 74377:94\|32 24.000 ns register " "Info: tco from clock \"/IOS\" to destination pin \"LC/D\" through register \"74377:94\|32\" is 24.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "/IOS source 19.000 ns + Longest register " "Info: + Longest clock path from clock \"/IOS\" to source register is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns /IOS 1 CLK PIN_21 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 6; CLK Node = '/IOS'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { /IOS } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 104 432 600 120 "/IOS" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns u11:109\|u1:94\|LCD~4 2 COMB LC51 12 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC51; Fanout = 12; COMB Node = 'u11:109\|u1:94\|LCD~4'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "9.000 ns" { /IOS u11:109|u1:94|LCD~4 } "NODE_NAME" } "" } } { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns 74377:94\|32 3 REG LC37 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94\|32'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "8.000 ns" { u11:109|u1:94|LCD~4 74377:94|32 } "NODE_NAME" } "" } } { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { 40 288 352 120 "32" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "19.000 ns" { /IOS u11:109|u1:94|LCD~4 74377:94|32 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { /IOS /IOS~out u11:109|u1:94|LCD~4 74377:94|32 } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { 40 288 352 120 "32" "" } } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74377:94\|32 1 REG LC37 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94\|32'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { 74377:94|32 } "NODE_NAME" } "" } } { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { 40 288 352 120 "32" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns LC/D 2 PIN PIN_31 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'LC/D'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "4.000 ns" { 74377:94|32 LC/D } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 632 1056 1232 648 "LC/D" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "4.000 ns" { 74377:94|32 LC/D } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { 74377:94|32 LC/D } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } } } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "19.000 ns" { /IOS u11:109|u1:94|LCD~4 74377:94|32 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { /IOS /IOS~out u11:109|u1:94|LCD~4 74377:94|32 } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "4.000 ns" { 74377:94|32 LC/D } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { 74377:94|32 LC/D } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A14 UD0 31.000 ns Longest " "Info: Longest tpd from source pin \"A14\" to destination pin \"UD0\" is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns A14 1 PIN PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_16; Fanout = 1; PIN Node = 'A14'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { A14 } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 232 432 600 248 "A14" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns u11:109\|u1:94\|UCS~6 2 COMB LC109 2 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC109; Fanout = 2; COMB Node = 'u11:109\|u1:94\|UCS~6'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "9.000 ns" { A14 u11:109|u1:94|UCS~6 } "NODE_NAME" } "" } } { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns u11:109\|u1:94\|UCS~9 3 COMB LC59 8 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC59; Fanout = 8; COMB Node = 'u11:109\|u1:94\|UCS~9'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "9.000 ns" { u11:109|u1:94|UCS~6 u11:109|u1:94|UCS~9 } "NODE_NAME" } "" } } { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(9.000 ns) 31.000 ns UD0 4 PIN PIN_134 0 " "Info: 4: + IC(2.000 ns) + CELL(9.000 ns) = 31.000 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'UD0'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "11.000 ns" { u11:109|u1:94|UCS~9 UD0 } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 472 320 496 488 "UD0" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.000 ns 80.65 % " "Info: Total cell delay = 25.000 ns ( 80.65 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 19.35 % " "Info: Total interconnect delay = 6.000 ns ( 19.35 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "31.000 ns" { A14 u11:109|u1:94|UCS~6 u11:109|u1:94|UCS~9 UD0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "31.000 ns" { A14 A14~out u11:109|u1:94|UCS~6 u11:109|u1:94|UCS~9 UD0 } { 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 7.000ns 9.000ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "74377:94\|32 CAP1/QEP1/IOPA3 /IOS 13.000 ns register " "Info: th for register \"74377:94\|32\" (data pin = \"CAP1/QEP1/IOPA3\", clock pin = \"/IOS\") is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "/IOS destination 19.000 ns + Longest register " "Info: + Longest clock path from clock \"/IOS\" to destination register is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns /IOS 1 CLK PIN_21 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 6; CLK Node = '/IOS'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { /IOS } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 104 432 600 120 "/IOS" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns u11:109\|u1:94\|LCD~4 2 COMB LC51 12 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC51; Fanout = 12; COMB Node = 'u11:109\|u1:94\|LCD~4'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "9.000 ns" { /IOS u11:109|u1:94|LCD~4 } "NODE_NAME" } "" } } { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns 74377:94\|32 3 REG LC37 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94\|32'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "8.000 ns" { u11:109|u1:94|LCD~4 74377:94|32 } "NODE_NAME" } "" } } { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { 40 288 352 120 "32" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "19.000 ns" { /IOS u11:109|u1:94|LCD~4 74377:94|32 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { /IOS /IOS~out u11:109|u1:94|LCD~4 74377:94|32 } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { 40 288 352 120 "32" "" } } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CAP1/QEP1/IOPA3 1 PIN PIN_27 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_27; Fanout = 1; PIN Node = 'CAP1/QEP1/IOPA3'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "" { CAP1/QEP1/IOPA3 } "NODE_NAME" } "" } } { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 632 472 672 648 "CAP1/QEP1/IOPA3" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns 74377:94\|32 2 REG LC37 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC37; Fanout = 1; REG Node = '74377:94\|32'" { } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "8.000 ns" { CAP1/QEP1/IOPA3 74377:94|32 } "NODE_NAME" } "" } } { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { 40 288 352 120 "32" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "10.000 ns" { CAP1/QEP1/IOPA3 74377:94|32 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { CAP1/QEP1/IOPA3 CAP1/QEP1/IOPA3~out 74377:94|32 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } } 0} } { { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "19.000 ns" { /IOS u11:109|u1:94|LCD~4 74377:94|32 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { /IOS /IOS~out u11:109|u1:94|LCD~4 74377:94|32 } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } { "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" "" { Report "D:/CPLDNEW/db/cpld4gdf00_cmp.qrpt" Compiler "cpld4gdf00" "UNKNOWN" "V1" "D:/CPLDNEW/db/cpld4gdf00.quartus_db" { Floorplan "D:/CPLDNEW/" "" "10.000 ns" { CAP1/QEP1/IOPA3 74377:94|32 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { CAP1/QEP1/IOPA3 CAP1/QEP1/IOPA3~out 74377:94|32 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 28 19:27:22 2005 " "Info: Processing ended: Wed Dec 28 19:27:22 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0} } { } 0}
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