cpld4gdf00.tan.qmsg

用maxplus2实现的一种通用逻辑模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 28 19:27:19 2005 " "Info: Processing started: Wed Dec 28 19:27:19 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cpld4gdf00 -c cpld4gdf00 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cpld4gdf00 -c cpld4gdf00" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "A0 " "Info: Assuming node \"A0\" is an undefined clock" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 344 432 600 360 "A0" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A1 " "Info: Assuming node \"A1\" is an undefined clock" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 312 432 600 328 "A1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A3 " "Info: Assuming node \"A3\" is an undefined clock" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 280 432 600 296 "A3" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A3" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A15 " "Info: Assuming node \"A15\" is an undefined clock" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 216 432 600 232 "A15" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A15" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A2 " "Info: Assuming node \"A2\" is an undefined clock" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 296 432 600 312 "A2" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "A2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "/IOS " "Info: Assuming node \"/IOS\" is an undefined clock" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 104 432 600 120 "/IOS" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "/IOS" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "u11:109\|u1:94\|LEDS~29 " "Info: Detected gated clock \"u11:109\|u1:94\|LEDS~29\" as buffer" {  } { { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u11:109\|u1:94\|LEDS~29" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "u11:109\|u1:94\|LCD~4 " "Info: Detected gated clock \"u11:109\|u1:94\|LCD~4\" as buffer" {  } { { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "u11:109\|u1:94\|LCD~4" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A0 " "Info: No valid register-to-register data paths exist for clock \"A0\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A1 " "Info: No valid register-to-register data paths exist for clock \"A1\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A3 " "Info: No valid register-to-register data paths exist for clock \"A3\"" {  } {  } 0}