cpld4gdf00.hier_info

用maxplus2实现的一种通用逻辑模块

|cpld4gdf00
/XFER <= u11:109./XFER
/DS => u11:109./DS
/PS => u11:109./PS
/IOS => u11:109./IOS
/RD => inst.DATAIN
/WE => inst1.DATAIN
SWRESET => u11:109.SWRESET
/PWRONRST => u11:109./PWRONRST
HOSTRESET => u11:109.HOSTRESET
TEFREST => u11:109.TEGREST
A15 => u11:109.A15
A14 => u11:109.A14
A13 => u11:109.A13
A12 => u11:109.A12
A3 => u11:109.A3
A2 => u11:109.A2
A1 => u11:109.A1
/STRB => u11:109./STRB
A0 => u11:109.A0
/UCS <= u11:109./UCS
/BUFFER <= u11:109./BUFFER
/RS <= u11:109./RS
/LRD <= 74377:94.Q3
CAP2/QEP2/IOPA4 => 74377:94.D2
CAP1/QEP1/IOPA3 => 74377:94.D1
CAP4/QEP3/IOPE7 => 74377:94.D4
CAP3/IOPA5 => 74377:94.D3
/LWR <= 74377:94.Q4
/LCE <= 74377:94.Q2
LC/D <= 74377:94.Q1
SD3 <= 74374:99.Q4
D0 <= 74244:68.2Y1
D1 <= 74244:68.2Y2
D2 <= 74244:68.2Y3
D3 <= 74244:68.2Y4
D4 <= 74244:68.1Y1
D5 <= 74244:68.1Y2
D6 <= 74244:68.1Y3
D7 <= 74244:68.1Y4
SD2 <= 74374:99.Q3
SD1 <= 74374:99.Q2
SD0 <= 74374:99.Q1
/DACS <= u11:109./DACS
/RAMWE <= u11:109./RAMWE
/RAMOE <= u11:109./RAMOE
/UOE <= u11:109./UOE
/UWE <= u11:109./UWE
INTSW <= 3.DB_MAX_OUTPUT_PORT_TYPE
SD7 => 2.IN0
SD7 => 74244:68.1A4
SD6 => 2.IN1
SD6 => 74244:68.1A3
SD5 => 2.IN2
SD5 => 74244:68.1A2
SD4 => 2.IN3
SD4 => 74244:68.1A1
UD7 <= TRI_GATE:129.b0
UD6 <= TRI_GATE:129.b1
UD5 <= TRI_GATE:129.b2
UD4 <= TRI_GATE:129.b3
UD3 <= TRI_GATE:129.b4
UD2 <= TRI_GATE:129.b5
UD1 <= TRI_GATE:129.b6
UD0 <= TRI_GATE:129.b7
BD5 <= TRI_GATE:76.b5
BD6 <= TRI_GATE:76.b6
BD7 <= TRI_GATE:76.b7
BD4 <= TRI_GATE:76.b4
BD1 <= TRI_GATE:76.b1
BD2 <= TRI_GATE:76.b2
BD3 <= TRI_GATE:76.b3
BD0 <= TRI_GATE:76.b0
L[1] <= 74273:69.Q1
L[2] <= 74273:69.Q2
L[3] <= 74273:69.Q3
L[4] <= 74273:69.Q4
L[5] <= 74273:69.Q5
L[6] <= 74273:69.Q6
L[7] <= 74273:69.Q7
L[8] <= 74273:69.Q8
RD[0] <= 74244:105.1Y1
RD[1] <= 74244:105.1Y2
RD[2] <= 74244:105.1Y3
RD[3] <= 74244:105.1Y4
RD[4] <= 74244:105.2Y1
RD[5] <= 74244:105.2Y2
RD[6] <= 74244:105.2Y3
RD[7] <= 74244:105.2Y4
K[0] => 74244:105.1A1
K[1] => 74244:105.1A2
K[2] => 74244:105.1A3
K[3] => 74244:105.1A4
K[4] => 74244:105.2A1
K[5] => 74244:105.2A2
K[6] => 74244:105.2A3
K[7] => 74244:105.2A4


|cpld4gdf00|u11:109
/XFER <= U1:94.XFER
/DS => U1:94.DS
/PS => U1:94.PS
/IOS => U1:94.IOS
/RD => U1:94.RD
/WE => U1:94.WE
SWRESET => U1:94.SWRESET
/PWRONRST => U1:94.PWRONRST
HOSTRESET => U1:94.HOSTRESET
TEGREST => U1:94.TRGREST
A15 => U1:94.A15
A14 => U1:94.A14
A13 => U1:94.A13
A12 => U1:94.A12
A3 => U1:94.A3
A2 => U1:94.A2
A1 => U1:94.A1
A0 => U1:94.A0
/UCS <= U1:94.UCS
/LCD <= U1:94.LCD
/BUFFER <= 67.DB_MAX_OUTPUT_PORT_TYPE
/STRB => 67.IN1
/LEDS <= U1:94.LEDS
/SWITCHES <= U1:94.SWITCHES
/DACS <= U1:94.DACS
INTRSW <= U1:94.INTRSW
/RS <= U1:94.RS
/UWE <= U1:94.UWE
/UOE <= U1:94.UOE
/RDSW <= U1:94.RDSW
/WRSW <= U1:94.WRSW
/RAMWE <= U1:94.RAMWE
/RAMOE <= U1:94.RAMOE


|cpld4gdf00|u11:109|U1:94
DS => RAMOE~0.IN0
PS => RAMOE~0.IN1
IOS => XFER~0.IN0
IOS => DACS~0.IN0
IOS => UOE~3.IN0
IOS => UCS~0.IN0
RD => RAMOE~1.IN0
RD => RDSW~0.IN0
RD => UOE~4.IN0
WE => RAMWE~0.IN0
WE => WRSW~6.IN0
WE => UWE~0.IN0
SWRESET => RS~1.IN0
PWRONRST => RS~0.IN0
HOSTRESET => RS~2.IN0
TRGREST => RS~3.IN0
A15 => XFER~1.IN0
A15 => DACS~0.IN1
A14 => UOE~0.IN0
A14 => UCS~1.IN0
A13 => UOE~1.IN0
A12 => UOE~2.IN0
A3 => XFER~3.IN0
A3 => DACS~1.IN0
A3 => WRSW~0.IN0
A3 => UCS~2.IN0
A2 => XFER~4.IN0
A2 => DACS~2.IN0
A2 => WRSW~2.IN0
A2 => LEDS~0.IN0
A2 => INTRSW~3.IN0
A2 => LCD~1.IN0
A2 => UCS~3.IN0
A1 => WRSW~3.IN0
A1 => INTRSW~4.IN0
A1 => LCD~2.IN0
A0 => WRSW~5.IN0
A0 => INTRSW~5.IN0
XFER <= XFER~6.DB_MAX_OUTPUT_PORT_TYPE
DACS <= DACS~2.DB_MAX_OUTPUT_PORT_TYPE
RAMOE <= RAMOE~1.DB_MAX_OUTPUT_PORT_TYPE
RAMWE <= RAMWE~0.DB_MAX_OUTPUT_PORT_TYPE
WRSW <= WRSW~8.DB_MAX_OUTPUT_PORT_TYPE
RDSW <= RDSW~2.DB_MAX_OUTPUT_PORT_TYPE
SWITCHES <= SWITCHES~0.DB_MAX_OUTPUT_PORT_TYPE
LEDS <= LEDS~1.DB_MAX_OUTPUT_PORT_TYPE
UOE <= UOE~4.DB_MAX_OUTPUT_PORT_TYPE
UWE <= UWE~0.DB_MAX_OUTPUT_PORT_TYPE
RS <= RS~3.DB_MAX_OUTPUT_PORT_TYPE
INTRSW <= INTRSW~6.DB_MAX_OUTPUT_PORT_TYPE
LCD <= LCD~3.DB_MAX_OUTPUT_PORT_TYPE
UCS <= UCS~3.DB_MAX_OUTPUT_PORT_TYPE


|cpld4gdf00|74377:94
Q4 <= 35.DB_MAX_OUTPUT_PORT_TYPE
D4 => 35.DATAIN
CLK => 35.CLK
CLK => 34.CLK
CLK => 33.CLK
CLK => 32.CLK
CLK => 30.CLK
CLK => 31.CLK
CLK => 29.CLK
CLK => 28.CLK
EN => 6.IN0
Q3 <= 34.DB_MAX_OUTPUT_PORT_TYPE
D3 => 34.DATAIN
Q2 <= 33.DB_MAX_OUTPUT_PORT_TYPE
D2 => 33.DATAIN
Q1 <= 32.DB_MAX_OUTPUT_PORT_TYPE
D1 => 32.DATAIN
Q5 <= 30.DB_MAX_OUTPUT_PORT_TYPE
D5 => 30.DATAIN
Q6 <= 31.DB_MAX_OUTPUT_PORT_TYPE
D6 => 31.DATAIN
Q7 <= 29.DB_MAX_OUTPUT_PORT_TYPE
D7 => 29.DATAIN
Q8 <= 28.DB_MAX_OUTPUT_PORT_TYPE
D8 => 28.DATAIN


|cpld4gdf00|74374:99
Q8 <= 47.DB_MAX_OUTPUT_PORT_TYPE
CLK => 20.CLK
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
D8 => 20.DATAIN
OEN => 2.IN0
Q7 <= 46.DB_MAX_OUTPUT_PORT_TYPE
D7 => 19.DATAIN
Q6 <= 45.DB_MAX_OUTPUT_PORT_TYPE
D6 => 18.DATAIN
Q5 <= 44.DB_MAX_OUTPUT_PORT_TYPE
D5 => 17.DATAIN
Q4 <= 43.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q3 <= 42.DB_MAX_OUTPUT_PORT_TYPE
D3 => 15.DATAIN
Q2 <= 41.DB_MAX_OUTPUT_PORT_TYPE
D2 => 14.DATAIN
Q1 <= 40.DB_MAX_OUTPUT_PORT_TYPE
D1 => 13.DATAIN


|cpld4gdf00|TRI_GATE:129
a0 => process0~0.DATAIN
a1 => process0~1.DATAIN
a2 => process0~2.DATAIN
a3 => process0~3.DATAIN
a4 => process0~4.DATAIN
a5 => process0~5.DATAIN
a6 => process0~6.DATAIN
a7 => process0~7.DATAIN
en => process0~0.OE
en => process0~1.OE
en => process0~2.OE
en => process0~3.OE
en => process0~4.OE
en => process0~5.OE
en => process0~6.OE
en => process0~7.OE
b0 <= process0~0.DB_MAX_OUTPUT_PORT_TYPE
b1 <= process0~1.DB_MAX_OUTPUT_PORT_TYPE
b2 <= process0~2.DB_MAX_OUTPUT_PORT_TYPE
b3 <= process0~3.DB_MAX_OUTPUT_PORT_TYPE
b4 <= process0~4.DB_MAX_OUTPUT_PORT_TYPE
b5 <= process0~5.DB_MAX_OUTPUT_PORT_TYPE
b6 <= process0~6.DB_MAX_OUTPUT_PORT_TYPE
b7 <= process0~7.DB_MAX_OUTPUT_PORT_TYPE


|cpld4gdf00|TRI_GATE:76
a0 => process0~0.DATAIN
a1 => process0~1.DATAIN
a2 => process0~2.DATAIN
a3 => process0~3.DATAIN
a4 => process0~4.DATAIN
a5 => process0~5.DATAIN
a6 => process0~6.DATAIN
a7 => process0~7.DATAIN
en => process0~0.OE
en => process0~1.OE
en => process0~2.OE
en => process0~3.OE
en => process0~4.OE
en => process0~5.OE
en => process0~6.OE
en => process0~7.OE
b0 <= process0~0.DB_MAX_OUTPUT_PORT_TYPE
b1 <= process0~1.DB_MAX_OUTPUT_PORT_TYPE
b2 <= process0~2.DB_MAX_OUTPUT_PORT_TYPE
b3 <= process0~3.DB_MAX_OUTPUT_PORT_TYPE
b4 <= process0~4.DB_MAX_OUTPUT_PORT_TYPE
b5 <= process0~5.DB_MAX_OUTPUT_PORT_TYPE
b6 <= process0~6.DB_MAX_OUTPUT_PORT_TYPE
b7 <= process0~7.DB_MAX_OUTPUT_PORT_TYPE


|cpld4gdf00|74244:68
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|cpld4gdf00|74273:69
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|cpld4gdf00|74244:105
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN