cpld4gdf00.map.qmsg

用maxplus2实现的一种通用逻辑模块

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a5 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a5\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a6 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a6\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a7 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a7\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74244 " "Info: Found entity 1: 74244" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74244 74244:68 " "Info: Elaborating entity \"74244\" for hierarchy \"74244:68\"" {  } { { "cpld4gdf00.bdf" "68" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 920 1024 1208 "68" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/others/maxplus2/74273.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74273.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74273 " "Info: Found entity 1: 74273" {  } { { "74273.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74273.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74273 74273:69 " "Info: Elaborating entity \"74273\" for hierarchy \"74273:69\"" {  } { { "cpld4gdf00.bdf" "69" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 224 1192 1312 416 "69" "" } } } }  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "74374:99\|43 " "Warning: Removed always-enabled tri-state buffer 74374:99\|43 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "74374:99\|42 " "Warning: Removed always-enabled tri-state buffer 74374:99\|42 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "74374:99\|41 " "Warning: Removed always-enabled tri-state buffer 74374:99\|41 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "74374:99\|40 " "Warning: Removed always-enabled tri-state buffer 74374:99\|40 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inst1 " "Warning: Converting TRI node \"inst1\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inst " "Warning: Converting TRI node \"inst\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "3 clear GND " "Warning: Reduced register \"3\" with stuck clear port to stuck value GND" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 1176 1240 1096 "3" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "74374:99\|16 " "Warning: No clock transition on register \"74374:99\|16\" due to stuck clock or clock enable" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 408 256 320 488 "16" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74374:99\|16 clock GND " "Warning: Reduced register \"74374:99\|16\" with stuck clock port to stuck value GND" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 408 256 320 488 "16" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "74374:99\|15 " "Warning: No clock transition on register \"74374:99\|15\" due to stuck clock or clock enable" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 304 256 320 384 "15" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74374:99\|15 clock GND " "Warning: Reduced register \"74374:99\|15\" with stuck clock port to stuck value GND" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 304 256 320 384 "15" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "74374:99\|14 " "Warning: No clock transition on register \"74374:99\|14\" due to stuck clock or clock enable" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 200 256 320 280 "14" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74374:99\|14 clock GND " "Warning: Reduced register \"74374:99\|14\" with stuck clock port to stuck value GND" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 200 256 320 280 "14" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "74374:99\|13 " "Warning: No clock transition on register \"74374:99\|13\" due to stuck clock or clock enable" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 96 256 320 176 "13" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "74374:99\|13 clock GND " "Warning: Reduced register \"74374:99\|13\" with stuck clock port to stuck value GND" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { 96 256 320 176 "13" "" } } } }  } 0}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "D0 " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"D0\" is moved to its source" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 816 512 688 832 "D0" "" } } } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "D1 " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"D1\" is moved to its source" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 832 512 688 848 "D1" "" } } } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "D2 " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"D2\" is moved to its source" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 848 512 688 864 "D2" "" } } } }  } 0} { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "D3 " "Info: Fanout of permanently enabled tri-state buffer feeding bidir \"D3\" is moved to its source" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 864 512 688 880 "D3" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_DISABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently disabled" { { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|1 " "Warning: Node \"74244:68\|1\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 64 296 344 96 "1" "" } } } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|6 " "Warning: Node \"74244:68\|6\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 112 296 344 144 "6" "" } } } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|10 " "Warning: Node \"74244:68\|10\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 160 296 344 192 "10" "" } } } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|11 " "Warning: Node \"74244:68\|11\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 208 296 344 240 "11" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|36 " "Warning: Node \"74244:68\|36\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 288 296 344 320 "36" "" } } } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|31 " "Warning: Node \"74244:68\|31\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 336 296 344 368 "31" "" } } } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|27 " "Warning: Node \"74244:68\|27\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 384 296 344 416 "27" "" } } } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "74244:68\|26 " "Warning: Node \"74244:68\|26\"" {  } { { "74244.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74244.bdf" { { 432 296 344 464 "26" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SD3 GND " "Warning: Pin \"SD3\" stuck at GND" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 864 1072 1248 880 "SD3" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SD2 GND " "Warning: Pin \"SD2\" stuck at GND" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 848 1072 1248 864 "SD2" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SD1 GND " "Warning: Pin \"SD1\" stuck at GND" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 832 1072 1248 848 "SD1" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SD0 GND " "Warning: Pin \"SD0\" stuck at GND" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 816 1072 1248 832 "SD0" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "/RAMWE VCC " "Warning: Pin \"/RAMWE\" stuck at VCC" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 136 848 1024 152 "/RAMWE" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "/RAMOE VCC " "Warning: Pin \"/RAMOE\" stuck at VCC" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 120 848 1024 136 "/RAMOE" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "/UOE VCC " "Warning: Pin \"/UOE\" stuck at VCC" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 216 888 1064 232 "/UOE" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "/UWE VCC " "Warning: Pin \"/UWE\" stuck at VCC" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 232 888 1064 248 "/UWE" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "INTSW GND " "Warning: Pin \"INTSW\" stuck at GND" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1032 1288 1464 1048 "INTSW" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "6 " "Warning: Design contains 6 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "/DS " "Warning: No output dependent on input pin \"/DS\"" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 72 432 600 88 "/DS" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "/PS " "Warning: No output dependent on input pin \"/PS\"" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 88 432 600 104 "/PS" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "/RD " "Warning: No output dependent on input pin \"/RD\"" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 120 64 232 136 "/RD" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "/WE " "Warning: No output dependent on input pin \"/WE\"" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 184 64 232 200 "/WE" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "A13 " "Warning: No output dependent on input pin \"A13\"" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 248 432 600 264 "A13" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "A12 " "Warning: No output dependent on input pin \"A12\"" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 264 432 600 280 "A12" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "152 " "Info: Implemented 152 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "34 " "Info: Implemented 34 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "26 " "Info: Implemented 26 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "32 " "Info: Implemented 32 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "59 " "Info: Implemented 59 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 59 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 59 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 28 19:27:05 2005 " "Info: Processing ended: Wed Dec 28 19:27:05 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}