cpld4gdf00.map.qmsg

用maxplus2实现的一种通用逻辑模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 28 19:26:52 2005 " "Info: Processing started: Wed Dec 28 19:26:52 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpld4gdf00 -c cpld4gdf00 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpld4gdf00 -c cpld4gdf00" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld4gdf.gdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpld4gdf.gdf" { { "Info" "ISGN_ENTITY_NAME" "1 cpld4gdf " "Info: Found entity 1: cpld4gdf" {  } { { "cpld4gdf.gdf" "" { Schematic "D:/CPLDNEW/cpld4gdf.gdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld4gdf00.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpld4gdf00.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 cpld4gdf00 " "Info: Found entity 1: cpld4gdf00" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cpld4gdf00 " "Info: Elaborating entity \"cpld4gdf00\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D6 74377 94 " "Warning: Port \"D6\" of type 74377 and instance \"94\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 600 944 1048 792 "94" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D5 74377 94 " "Warning: Port \"D5\" of type 74377 and instance \"94\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 600 944 1048 792 "94" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D8 74377 94 " "Warning: Port \"D8\" of type 74377 and instance \"94\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 600 944 1048 792 "94" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D7 74377 94 " "Warning: Port \"D7\" of type 74377 and instance \"94\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 600 944 1048 792 "94" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2A1 74244 68 " "Warning: Port \"2A1\" of type 74244 and instance \"68\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 920 1024 1208 "68" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2GN 74244 68 " "Warning: Port \"2GN\" of type 74244 and instance \"68\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 920 1024 1208 "68" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2A3 74244 68 " "Warning: Port \"2A3\" of type 74244 and instance \"68\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 920 1024 1208 "68" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2A2 74244 68 " "Warning: Port \"2A2\" of type 74244 and instance \"68\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 920 1024 1208 "68" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2A4 74244 68 " "Warning: Port \"2A4\" of type 74244 and instance \"68\" is missing source signal" {  } { { "cpld4gdf00.bdf" "" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 1016 920 1024 1208 "68" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "u11.gdf 1 1 " "Info: Using design file u11.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 u11 " "Info: Found entity 1: u11" {  } { { "u11.gdf" "" { Schematic "D:/CPLDNEW/u11.gdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "u11 u11:109 " "Info: Elaborating entity \"u11\" for hierarchy \"u11:109\"" {  } { { "cpld4gdf00.bdf" "109" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 56 608 800 376 "109" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "U1.vhd 2 1 " "Info: Using design file U1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 u1-u1_data " "Info: Found design unit 1: u1-u1_data" {  } { { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 u1 " "Info: Found entity 1: u1" {  } { { "U1.vhd" "" { Text "D:/CPLDNEW/U1.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "U1 u11:109\|U1:94 " "Info: Elaborating entity \"U1\" for hierarchy \"u11:109\|U1:94\"" {  } { { "u11.gdf" "94" { Schematic "D:/CPLDNEW/u11.gdf" { { 368 272 456 672 "94" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74377 " "Info: Found entity 1: 74377" {  } { { "74377.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74377.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74377 74377:94 " "Info: Elaborating entity \"74377\" for hierarchy \"74377:94\"" {  } { { "cpld4gdf00.bdf" "94" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 600 944 1048 792 "94" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74374 " "Info: Found entity 1: 74374" {  } { { "74374.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74374.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74374 74374:99 " "Info: Elaborating entity \"74374\" for hierarchy \"74374:99\"" {  } { { "cpld4gdf00.bdf" "99" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 800 944 1064 992 "99" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "TRI_GATE.vhd 2 1 " "Info: Using design file TRI_GATE.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tri_gate-behav " "Info: Found design unit 1: tri_gate-behav" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tri_gate " "Info: Found entity 1: tri_gate" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TRI_GATE TRI_GATE:129 " "Info: Elaborating entity \"TRI_GATE\" for hierarchy \"TRI_GATE:129\"" {  } { { "cpld4gdf00.bdf" "129" { Schematic "D:/CPLDNEW/cpld4gdf00.bdf" { { 440 504 608 616 "129" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a0 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a1 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a2 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a3 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a4 TRI_GATE.vhd(17) " "Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal \"a4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "TRI_GATE.vhd" "" { Text "D:/CPLDNEW/TRI_GATE.vhd" 17 0 0 } }  } 0}