u1.vhd

用maxplus2实现的一种通用逻辑模块

library ieee;
use ieee.std_logic_1164.all;
entity u1 is
    port(DS,PS,IOS,RD,WE,SWRESET,PWRONRST,HOSTRESET,TRGREST,A15,A14,A13,A12,A3,A2,A1,A0:in std_logic;
         XFER,DACS,RAMOE,RAMWE,WRSW,RDSW,SWITCHES,LEDS,UOE,UWE,RS,INTRSW,LCD,UCS,SWCE,CDR,CDW:out std_logic
         );
end u1;

architecture u1_data of u1 is
    begin
        XFER<=NOT(NOT(IOS) AND NOT(A15) AND A3 AND NOT(A2));
        DACS<=IOS OR A15 OR A3 OR A2;
        RAMOE<=RD OR (DS AND PS);
        RAMWE<=WE OR (DS AND PS);
        SWCE<=NOT(NOT(IOS) AND NOT(A15) AND NOT(A3) AND A2 AND NOT(A1) AND A0); 
        WRSW<=NOT(NOT(IOS) AND NOT(A15) AND NOT(A3) AND A2 AND NOT(A1) AND A0)OR WE;
        RDSW<=NOT(NOT(IOS) AND NOT(A15) AND NOT(A3) AND A2 AND NOT(A1) AND A0) OR RD;
        SWITCHES<=NOT(NOT(IOS) AND NOT(A15) AND A3 AND NOT(A2)AND A1 AND A0);
        LEDS<=NOT(NOT(IOS) AND NOT(A15) AND A3 AND A2);
        UOE<=NOT(A15) OR A14 OR A13 OR A12 OR IOS OR RD;
        UWE<=NOT(A15) OR A14 OR A13 OR A12 OR IOS OR WE;
        RS<=NOT(SWRESET);
        INTRSW<=NOT(WE) AND NOT(IOS) AND NOT(A15) AND NOT(A3) AND A2 AND A1 AND NOT(A0);
        LCD<=NOT(IOS OR A15 OR NOT(A3) OR A2 OR A1);
        UCS<=NOT(IOS OR NOT(A15) OR A14 OR A3 OR A2); 
        CDR<=IOS OR A15 OR NOT(A3) OR A2 OR A1 OR NOT(A0) OR RD;
        CDW<=IOS OR A15 OR NOT(A3) OR A2 OR A1 OR NOT(A0) OR WE;
    end u1_data;