cpld4gdf00.map.eqn

用maxplus2实现的一种通用逻辑模块

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- (including device programming or simulation files), and any 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L87 is K[7]~16
A1L87_or_out = K[7];
A1L87 = A1L87_or_out;


--H1L6 is u11:109|u1:94|XFER~38
H1L6_p1_out = A3 & !A15 & !A2 & !/IOS;
H1L6_or_out = H1L6_p1_out;
H1L6 = !(H1L6_or_out);


--A1L67 is K[6]~18
A1L67_or_out = K[6];
A1L67 = A1L67_or_out;


--A1L47 is K[5]~20
A1L47_or_out = K[5];
A1L47 = A1L47_or_out;


--A1L27 is K[4]~22
A1L27_or_out = K[4];
A1L27 = A1L27_or_out;


--A1L07 is K[3]~24
A1L07_or_out = K[3];
A1L07 = A1L07_or_out;


--A1L86 is K[2]~26
A1L86_or_out = K[2];
A1L86 = A1L86_or_out;


--A1L66 is K[1]~28
A1L66_or_out = K[1];
A1L66 = A1L66_or_out;


--A1L46 is K[0]~30
A1L46_or_out = K[0];
A1L46 = A1L46_or_out;


--H1L4 is u11:109|u1:94|RS~28
H1L4_p1_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
H1L4_or_out = H1L4_p1_out;
H1L4 = !(H1L4_or_out);


--A1L111 is SD4~2
A1L111_or_out = SD4;
A1L111 = A1L111_or_out;


--A1L311 is SD5~2
A1L311_or_out = SD5;
A1L311 = A1L311_or_out;


--A1L511 is SD6~2
A1L511_or_out = SD6;
A1L511 = A1L511_or_out;


--A1L711 is SD7~2
A1L711_or_out = SD7;
A1L711 = A1L711_or_out;


--H1L5 is u11:109|u1:94|UCS~6
H1L5_p1_out = !A3 & A15 & !A2 & !/IOS & !A14;
H1L5_or_out = H1L5_p1_out;
H1L5 = !(H1L5_or_out);


--H1L1 is u11:109|u1:94|DACS~5
H1L1_p1_out = !A3 & !A15 & !A2 & !/IOS;
H1L1_or_out = H1L1_p1_out;
H1L1 = !(H1L1_or_out);


--H1L2 is u11:109|u1:94|LCD~4
H1L2_p1_out = A0 & !A1 & A3 & !A15 & !A2 & !/IOS;
H1L2_or_out = H1L2_p1_out;
H1L2 = H1L2_or_out;


--A1L64 is D4~5
A1L64_or_out = A1L54;
A1L64 = A1L64_or_out;


--A1L05 is D5~5
A1L05_or_out = A1L94;
A1L05 = A1L05_or_out;


--A1L45 is D6~5
A1L45_or_out = A1L35;
A1L45 = A1L45_or_out;


--A1L85 is D7~5
A1L85_or_out = A1L75;
A1L85 = A1L85_or_out;


--A1L15 is D5~7
A1L15_or_out = A1L94;
A1L15 = A1L15_or_out;


--A1L55 is D6~7
A1L55_or_out = A1L35;
A1L55 = A1L55_or_out;


--A1L95 is D7~7
A1L95_or_out = A1L75;
A1L95 = A1L95_or_out;


--A1L74 is D4~7
A1L74_or_out = A1L54;
A1L74 = A1L74_or_out;


--G1L1 is u11:109|67~9
G1L1_p1_out = A3 & !A2 & H1L6;
G1L1_p2_out = H1L6 & A15;
G1L1_p3_out = !A3 & A2 & H1L6;
G1L1_p4_out = H1L6 & /IOS;
G1L1_or_out = /STRB # G1L1_p1_out # G1L1_p2_out # G1L1_p3_out # G1L1_p4_out;
G1L1 = G1L1_or_out;


--E1_35 is 74377:94|35
E1_35_or_out = CAP4/QEP3/IOPE7;
E1_35_reg_input = E1_35_or_out;
E1_35 = DFFE(E1_35_reg_input, !H1L2, , , );


--E1_34 is 74377:94|34
E1_34_or_out = CAP3/IOPA5;
E1_34_reg_input = E1_34_or_out;
E1_34 = DFFE(E1_34_reg_input, !H1L2, , , );


--E1_33 is 74377:94|33
E1_33_or_out = CAP2/QEP2/IOPA4;
E1_33_reg_input = E1_33_or_out;
E1_33 = DFFE(E1_33_reg_input, !H1L2, , , );


--E1_32 is 74377:94|32
E1_32_or_out = CAP1/QEP1/IOPA3;
E1_32_reg_input = E1_32_or_out;
E1_32 = DFFE(E1_32_reg_input, !H1L2, , , );


--C1_19 is 74273:69|19
C1_19_or_out = A1L501;
C1_19_reg_input = C1_19_or_out;
C1_19_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_19 = DFFE(C1_19_reg_input, H1L3, !C1_19_p2_out, , );


--H1L3 is u11:109|u1:94|LEDS~29
H1L3 = EXP(A3 & !A15 & A2 & !/IOS);


--C1_18 is 74273:69|18
C1_18_or_out = A1L401;
C1_18_reg_input = C1_18_or_out;
C1_18_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_18 = DFFE(C1_18_reg_input, H1L3, !C1_18_p2_out, , );


--C1_17 is 74273:69|17
C1_17_or_out = A1L301;
C1_17_reg_input = C1_17_or_out;
C1_17_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_17 = DFFE(C1_17_reg_input, H1L3, !C1_17_p2_out, , );


--C1_16 is 74273:69|16
C1_16_or_out = A1L201;
C1_16_reg_input = C1_16_or_out;
C1_16_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_16 = DFFE(C1_16_reg_input, H1L3, !C1_16_p2_out, , );


--C1_15 is 74273:69|15
C1_15_or_out = A1L101;
C1_15_reg_input = C1_15_or_out;
C1_15_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_15 = DFFE(C1_15_reg_input, H1L3, !C1_15_p2_out, , );


--C1_14 is 74273:69|14
C1_14_or_out = A1L001;
C1_14_reg_input = C1_14_or_out;
C1_14_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_14 = DFFE(C1_14_reg_input, H1L3, !C1_14_p2_out, , );


--C1_13 is 74273:69|13
C1_13_or_out = A1L99;
C1_13_reg_input = C1_13_or_out;
C1_13_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_13 = DFFE(C1_13_reg_input, H1L3, !C1_13_p2_out, , );


--C1_12 is 74273:69|12
C1_12_or_out = A1L89;
C1_12_reg_input = C1_12_or_out;
C1_12_p2_out = !TEFREST & !HOSTRESET & !SWRESET & /PWRONRST;
C1_12 = DFFE(C1_12_reg_input, H1L3, !C1_12_p2_out, , );


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--~GND~3 is ~GND~3
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~VCC~2 is ~VCC~2
~VCC~2_or_out = GND;
~VCC~2 = !(~VCC~2_or_out);


--~VCC~3 is ~VCC~3
~VCC~3_or_out = GND;
~VCC~3 = !(~VCC~3_or_out);


--~GND~4 is ~GND~4
~GND~4_or_out = GND;
~GND~4 = ~GND~4_or_out;


--~VCC~4 is ~VCC~4
~VCC~4_or_out = GND;
~VCC~4 = !(~VCC~4_or_out);


--~VCC~5 is ~VCC~5
~VCC~5_or_out = GND;
~VCC~5 = !(~VCC~5_or_out);


--~VCC~6 is ~VCC~6
~VCC~6_or_out = GND;
~VCC~6 = !(~VCC~6_or_out);


--~VCC~7 is ~VCC~7
~VCC~7_or_out = GND;
~VCC~7 = !(~VCC~7_or_out);


--~VCC~8 is ~VCC~8
~VCC~8_or_out = GND;
~VCC~8 = !(~VCC~8_or_out);


--~VCC~9 is ~VCC~9
~VCC~9_or_out = GND;
~VCC~9 = !(~VCC~9_or_out);


--~VCC~10 is ~VCC~10
~VCC~10_or_out = GND;
~VCC~10 = !(~VCC~10_or_out);


--~VCC~11 is ~VCC~11
~VCC~11_or_out = GND;
~VCC~11 = !(~VCC~11_or_out);


--~VCC~12 is ~VCC~12
~VCC~12_or_out = GND;
~VCC~12 = !(~VCC~12_or_out);


--~VCC~13 is ~VCC~13
~VCC~13_or_out = GND;
~VCC~13 = !(~VCC~13_or_out);


--~VCC~14 is ~VCC~14
~VCC~14_or_out = GND;
~VCC~14 = !(~VCC~14_or_out);


--~VCC~15 is ~VCC~15
~VCC~15_or_out = GND;
~VCC~15 = !(~VCC~15_or_out);


--/DS is /DS
--operation mode is input

/DS = INPUT();


--/PS is /PS
--operation mode is input

/PS = INPUT();


--/IOS is /IOS
--operation mode is input

/IOS = INPUT();


--/RD is /RD
--operation mode is input

/RD = INPUT();


--/WE is /WE
--operation mode is input

/WE = INPUT();


--SWRESET is SWRESET
--operation mode is input

SWRESET = INPUT();


--/PWRONRST is /PWRONRST
--operation mode is input

/PWRONRST = INPUT();


--HOSTRESET is HOSTRESET
--operation mode is input

HOSTRESET = INPUT();


--TEFREST is TEFREST
--operation mode is input

TEFREST = INPUT();


--A15 is A15
--operation mode is input

A15 = INPUT();


--A14 is A14
--operation mode is input

A14 = INPUT();


--A13 is A13
--operation mode is input

A13 = INPUT();


--A12 is A12
--operation mode is input

A12 = INPUT();


--A3 is A3
--operation mode is input

A3 = INPUT();


--A2 is A2
--operation mode is input

A2 = INPUT();


--A1 is A1
--operation mode is input

A1 = INPUT();


--/STRB is /STRB
--operation mode is input

/STRB = INPUT();


--A0 is A0
--operation mode is input

A0 = INPUT();


--CAP2/QEP2/IOPA4 is CAP2/QEP2/IOPA4
--operation mode is input

CAP2/QEP2/IOPA4 = INPUT();


--CAP1/QEP1/IOPA3 is CAP1/QEP1/IOPA3
--operation mode is input

CAP1/QEP1/IOPA3 = INPUT();


--CAP4/QEP3/IOPE7 is CAP4/QEP3/IOPE7
--operation mode is input

CAP4/QEP3/IOPE7 = INPUT();


--CAP3/IOPA5 is CAP3/IOPA5
--operation mode is input

CAP3/IOPA5 = INPUT();


--SD7 is SD7
--operation mode is input

SD7 = INPUT();


--SD6 is SD6
--operation mode is input

SD6 = INPUT();


--SD5 is SD5
--operation mode is input

SD5 = INPUT();


--SD4 is SD4
--operation mode is input