tri.tdf

用maxplus2实现的一种通用逻辑模块

library ieee;
use ieee.std_logic_1164.all;

entity tri_gate is
    port(a0,a1,a2,a3,a4,a5,a6,a7,:in std_logic;
         en:in std_logic; 
         b0,b1,b2,b3,b4,b5,b6,b7:out std_logic;
         
end tri_gate;

architecture behav of tri_gate is
   begin
        process
          begin
               if en='1' then
                  b0<=a0;b1<=a1;b2<=a2;b3<=a3;b4<=a4;b5<=a5;b6<=a6;b7<=a7
               else
                  b0<='Z';b1<='Z';b2<='Z';b3<='Z';b4<='Z';b5<='Z';b6<='Z';b7<='Z';
               end if;
        end process;
end behav;