cpld4gdf00.map.rpt

用maxplus2实现的一种通用逻辑模块

; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name       ;
+----------------------------+------------+------+---------------------------+
; |cpld4gdf00                ; 59         ; 92   ; |cpld4gdf00               ;
;    |74273:69|              ; 8          ; 0    ; |cpld4gdf00|74273:69      ;
;    |74377:94|              ; 4          ; 0    ; |cpld4gdf00|74377:94      ;
;    |u11:109|               ; 6          ; 0    ; |cpld4gdf00|u11:109       ;
;       |u1:94|              ; 5          ; 0    ; |cpld4gdf00|u11:109|u1:94 ;
+----------------------------+------------+------+---------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/CPLDNEW/cpld4gdf00.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 28 19:26:52 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpld4gdf00 -c cpld4gdf00
Info: Found 1 design units, including 1 entities, in source file cpld4gdf.gdf
    Info: Found entity 1: cpld4gdf
Info: Found 1 design units, including 1 entities, in source file cpld4gdf00.bdf
    Info: Found entity 1: cpld4gdf00
Info: Elaborating entity "cpld4gdf00" for the top level hierarchy
Warning: Port "D6" of type 74377 and instance "94" is missing source signal
Warning: Port "D5" of type 74377 and instance "94" is missing source signal
Warning: Port "D8" of type 74377 and instance "94" is missing source signal
Warning: Port "D7" of type 74377 and instance "94" is missing source signal
Warning: Port "2A1" of type 74244 and instance "68" is missing source signal
Warning: Port "2GN" of type 74244 and instance "68" is missing source signal
Warning: Port "2A3" of type 74244 and instance "68" is missing source signal
Warning: Port "2A2" of type 74244 and instance "68" is missing source signal
Warning: Port "2A4" of type 74244 and instance "68" is missing source signal
Info: Using design file u11.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: u11
Info: Elaborating entity "u11" for hierarchy "u11:109"
Info: Using design file U1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: u1-u1_data
    Info: Found entity 1: u1
Info: Elaborating entity "U1" for hierarchy "u11:109|U1:94"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74377.bdf
    Info: Found entity 1: 74377
Info: Elaborating entity "74377" for hierarchy "74377:94"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74374.bdf
    Info: Found entity 1: 74374
Info: Elaborating entity "74374" for hierarchy "74374:99"
Info: Using design file TRI_GATE.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: tri_gate-behav
    Info: Found entity 1: tri_gate
Info: Elaborating entity "TRI_GATE" for hierarchy "TRI_GATE:129"
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at TRI_GATE.vhd(17): signal "a7" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74244.bdf
    Info: Found entity 1: 74244
Info: Elaborating entity "74244" for hierarchy "74244:68"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74273.bdf
    Info: Found entity 1: 74273
Info: Elaborating entity "74273" for hierarchy "74273:69"
Warning: Removed always-enabled tri-state buffer 74374:99|43 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer 74374:99|42 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer 74374:99|41 feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer 74374:99|40 feeding logic, open-drain buffer or output pin
Warning: Converting TRI node "inst1" that feeds logic to an OR gate
Warning: Converting TRI node "inst" that feeds logic to an OR gate
Warning: Reduced register "3" with stuck clear port to stuck value GND
Warning: No clock transition on register "74374:99|16" due to stuck clock or clock enable
Warning: Reduced register "74374:99|16" with stuck clock port to stuck value GND
Warning: No clock transition on register "74374:99|15" due to stuck clock or clock enable
Warning: Reduced register "74374:99|15" with stuck clock port to stuck value GND
Warning: No clock transition on register "74374:99|14" due to stuck clock or clock enable
Warning: Reduced register "74374:99|14" with stuck clock port to stuck value GND
Warning: No clock transition on register "74374:99|13" due to stuck clock or clock enable
Warning: Reduced register "74374:99|13" with stuck clock port to stuck value GND
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "D0" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "D1" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "D2" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "D3" is moved to its source
Warning: TRI or OPNDRN buffers permanently disabled
    Warning: Node "74244:68|1"
    Warning: Node "74244:68|6"
    Warning: Node "74244:68|10"
    Warning: Node "74244:68|11"
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "74244:68|36"
    Warning: Node "74244:68|31"
    Warning: Node "74244:68|27"
    Warning: Node "74244:68|26"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SD3" stuck at GND
    Warning: Pin "SD2" stuck at GND
    Warning: Pin "SD1" stuck at GND
    Warning: Pin "SD0" stuck at GND
    Warning: Pin "/RAMWE" stuck at VCC
    Warning: Pin "/RAMOE" stuck at VCC
    Warning: Pin "/UOE" stuck at VCC
    Warning: Pin "/UWE" stuck at VCC
    Warning: Pin "INTSW" stuck at GND
Warning: Design contains 6 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "/DS"
    Warning: No output dependent on input pin "/PS"
    Warning: No output dependent on input pin "/RD"
    Warning: No output dependent on input pin "/WE"
    Warning: No output dependent on input pin "A13"
    Warning: No output dependent on input pin "A12"
Info: Implemented 152 device resources after synthesis - the final resource count might be different
    Info: Implemented 34 input pins
    Info: Implemented 26 output pins
    Info: Implemented 32 bidirectional pins
    Info: Implemented 59 macrocells
    Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 59 warnings
    Info: Processing ended: Wed Dec 28 19:27:05 2005
    Info: Elapsed time: 00:00:14