hc245.vhd

来自「用maxplus2实现的一种通用逻辑模块」· VHDL 代码 · 共 15 行

library ieee; 
use ieee.Std_logic_1164.all;

entity HC245 is
    port(A, B : inout std_logic_vector(7 downto 0);
         DIR, GBAR : in std_logic
         );
end HC245;

architecture ver of HC245 is
begin
 A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');
 B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');
end ver;