count4.txt

VHDL源代码.设计一个模为4的计数器

设计一个模为4的计数器，并在实验箱上用七段数码管显示结果
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count40 is
port(enable:in std_logic;
     clk:in std_logic;
     seg:out std_logic_vector(6 downto 0);
     y:out std_logic_vector(2 downto 0));
end count40;
 
architecture rt1 of count40 is
signal q_tmp:std_logic_vector(1 downto 0);
begin

p1:process(clk)
begin
if(clk'event and clk='1')then
   if(enable='1')then
        if(q_tmp="11")then
            q_tmp<="00";
        else
            q_tmp<=q_tmp+1;
        end if;
   end if;
end process p1;

p2:process(q_tmp)
begin
case q_tmp is
            when"00"=>seg<="0111111";
            when"01"=>seg<="0000110";
            when"10"=>seg<="1011011";
            when"11"=>seg<="1001111";
            when others=>seg<="xxxxxxx";
end case;
end process p2;
y<="000";
end rt1;