vz_ver4.pdf

该工程文件实现ARM系统中CPLD的逻辑工作

[project]
name=vz_ver4
netlist=d:\cpld_p~1\vz_ver4\vz_ver4.alb
contents=vz_ver4
date=11/29/02
time=16:28:57
version=3.1.4.05.97
generics=MAX
Type=F21i
FndType=F3.1i
top_level=schematic
library_net=ON
sim_mode=FUNC
pdf_dir=e:\张全\数字语音\终端cp~1\
lib_order=1001 133 161

[libraries]
1001=
133=d:\fndtn\active\syslib\simprims
161=d:\fndtn\active\syslib\xc9500

[xilinx]
libraries=unified
family=5
xact9=On
xfam=XC9500XL

[device]
xilinx=9536-10XLVQ44
part=9536XLVQ44-10

[netlist]
external=FALSE

[Schematic]
Table01=Project
Table02=Sheet
Table03=Date
Table04=Date Last Modified

[sheets]
vz_ver41=

[Log]
imp_EDIF.log=Import EDIF netlist
netlist.log=Simulator Netlist Log
exp_EDIF.log=Export netlist to EDIF 200

[timings]
vz_ver4=

[OpenDoc]

[implement_HDL]
family=5
xfam=XC9500XL
part=9536XLVQ44-10
xilinx=9536-10XLVQ44

[LOGI_MACRO]
CLK_DIV=CLK_DIV.mod

[FILE7]
macro_update=DE
DE=de.abl
scan_time=1039481645

[APP_95]
lid=0
oid=0
source=E:\张全\数字语音\终端CP~1\VZ_VER4\vz_ver41.sch



[EDIF_MACRO]
error=1
macro_empty=DE

[implement_XIE]
version=ver1
revision=rev1


[OPEN32]
lpstrInitialDir=D:\XILINX\ACTIVE\PROJECTS
lpstrTitle=Browse
Flags=3
cmdLine=-b -h 868 -hp 842 -m PCM_BROWSE32_MESSAGE -f D:\XILINX\ACTIVE\PROJECTS\current.pdf