myfifo.map.rpt

VERILOG HDL 实际工控项目源码

+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                              ;
+-------------------------------------------------------------------+-----------------+
; File Name                                                         ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; myfifo.bdf                                                        ; yes             ;
; mydram.v                                                          ; yes             ;
; watchdog.v                                                        ; yes             ;
; ad_collect.v                                                      ; yes             ;
; addr_code.v                                                       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc      ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/flex10ke_lcell.inc    ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/addcore.inc           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/addcore.tdf           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altshift.tdf          ; yes             ;
+-------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 483     ;
; Total combinational functions     ; 330     ;
; Total 4-input functions           ; 236     ;
; Total 3-input functions           ; 31      ;
; Total 2-input functions           ; 14      ;
; Total 1-input functions           ; 47      ;
; Total 0-input functions           ; 2       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 222     ;
; Total logic cells in carry chains ; 49      ;
; I/O pins                          ; 91      ;
; Maximum fan-out node              ; g_clk   ;
; Maximum fan-out                   ; 206     ;
; Total fan-out                     ; 1780    ;
; Average fan-out                   ; 3.10    ;
+-----------------------------------+---------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 11    ;
; Number of synthesis-generated cells                    ; 472   ;
; Number of WYSIWYG LUTs                                 ; 11    ;
; Number of synthesis-generated LUTs                     ; 319   ;
; Number of WYSIWYG registers                            ; 11    ;
; Number of synthesis-generated registers                ; 211   ;
; Number of cells with combinational logic only          ; 261   ;
; Number of cells with registers only                    ; 153   ;
; Number of cells with combinational logic and registers ; 69    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 11    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 50    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 114   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version
    Info: Processing started: Thu Oct 14 17:16:51 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off myfifo -c myfifo
Info: Found 1 design units, including 1 entities, in source file myfifo.bdf
    Info: Found entity 1: myfifo
Info: Found 1 design units, including 1 entities, in source file mydram.v
    Info: Found entity 1: mydram
Info: Found 1 design units, including 1 entities, in source file wram.v
    Info: Found entity 1: wram
Info: Found 1 design units, including 1 entities, in source file watchdog.v
    Info: Found entity 1: watchdog
Info: Found 1 design units, including 1 entities, in source file ad_collect.v
    Info: Found entity 1: ad_collect
Info: Found 1 design units, including 1 entities, in source file addr_code.v
    Info: Found entity 1: addr_code
Warning: Verilog HDL expression warning at ad_collect.v(139): truncated operand with size 13 to match size of smaller operand (12)
Warning: Verilog HDL expression warning at ad_collect.v(159): truncated operand with size 4 to match size of smaller operand (3)
Warning: Verilog HDL expression warning at ad_collect.v(167): truncated operand with size 3 to match size of smaller operand (2)
Warning: Verilog HDL Always Construct warning at ad_collect.v(85): variable ad_sel may not be assigned a new value in every possible path through the Always Construct.  Variable ad_sel holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at ad_collect.v(85): variable ad_sl may not be assigned a new value in every possible path through the Always Construct.  Variable ad_sl holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at ad_collect.v(85): variable ad_wr may not be assigned a new value in every possible path through the Always Construct.  Variable ad_wr holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL expression warning at ad_collect.v(193): truncated operand with size 12 to match size of smaller operand (11)
Warning: Verilog HDL expression warning at watchdog.v(99): truncated operand with size 27 to match size of smaller operand (26)
Warning: Verilog HDL expression warning at watchdog.v(114): truncated operand with size 27 to match size of smaller operand (26)
Warning: Verilog HDL Always Construct warning at mydram.v(78): variable rd_addr is used in Always Construct, but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at mydram.v(78): variable coll_mem is used in Always Construct, but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at mydram.v(75): variable d_out may not be assigned a new value in every possible path through the Always Construct.  Variable d_out holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL expression warning at mydram.v(87): truncated operand with size 16 to match size of smaller operand (14)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: ad_collect:inst1|int_reg[0]~55
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine |myfifo|watchdog:inst|step contains 4 states and 0 state bits
Info: State machine |myfifo|ad_collect:inst1|step contains 9 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |myfifo|watchdog:inst|step
Info: Encoding result for state machine |myfifo|watchdog:inst|step
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit watchdog:inst|step~21
        Info: Encoded state bit watchdog:inst|step~20
        Info: Encoded state bit watchdog:inst|step~19
        Info: Encoded state bit watchdog:inst|step~18
    Info: State |myfifo|watchdog:inst|step.00 uses code string 0000
    Info: State |myfifo|watchdog:inst|step.10 uses code string 0011
    Info: State |myfifo|watchdog:inst|step.01 uses code string 0101
    Info: State |myfifo|watchdog:inst|step.11 uses code string 1001
Info: Selected Auto state machine encoding method for state machine |myfifo|ad_collect:inst1|step
Info: Encoding result for state machine |myfifo|ad_collect:inst1|step
    Info: Completed encoding using 9 state bits
        Info: Encoded state bit ad_collect:inst1|step~67
        Info: Encoded state bit ad_collect:inst1|step~66
        Info: Encoded state bit ad_collect:inst1|step~65
        Info: Encoded state bit ad_collect:inst1|step~64
        Info: Encoded state bit ad_collect:inst1|step~63
        Info: Encoded state bit ad_collect:inst1|step~62
        Info: Encoded state bit ad_collect:inst1|step~61
        Info: Encoded state bit ad_collect:inst1|step~60
        Info: Encoded state bit ad_collect:inst1|step~59
    Info: State |myfifo|ad_collect:inst1|step.0000 uses code string 000000000
    Info: State |myfifo|ad_collect:inst1|step.0111 uses code string 000000110
    Info: State |myfifo|ad_collect:inst1|step.0110 uses code string 000001010
    Info: State |myfifo|ad_collect:inst1|step.0101 uses code string 000010010
    Info: State |myfifo|ad_collect:inst1|step.0100 uses code string 000100010
    Info: State |myfifo|ad_collect:inst1|step.0011 uses code string 001000010
    Info: State |myfifo|ad_collect:inst1|step.0010 uses code string 010000010
    Info: State |myfifo|ad_collect:inst1|step.0001 uses code string 100000010
    Info: State |myfifo|ad_collect:inst1|step.1000 uses code string 000000011
Warning: Output pins are stuck at VCC or GND
    Warning: Pin ad_wr stuck at VCC
    Warning: Pin ad_sel stuck at GND
    Warning: Pin bus2_dir stuck at GND
    Warning: Pin dsp_tck0 stuck at VCC
    Warning: Pin dsp_tck1 stuck at VCC
    Warning: Pin bus2_ce stuck at GND
    Warning: Pin ad_sl[3] stuck at VCC
    Warning: Pin ad_sl[2] stuck at VCC
    Warning: Pin ad_sl[1] stuck at VCC
    Warning: Pin ad_sl[0] stuck at VCC
Info: Registers with preset signals will power-up high
Warning: Design contains 6 input pin(s) that do not drive logic
    Warning: No output dependent on input pin page[0]
    Warning: No output dependent on input pin ad_busy
    Warning: No output dependent on input pin rd_addr[7]
    Warning: No output dependent on input pin rd_addr[6]
    Warning: No output dependent on input pin rd_addr[5]
    Warning: No output dependent on input pin rd_addr[4]
Info: Implemented 574 device resources after synthesis - the final resource count might be different
    Info: Implemented 43 input pins
    Info: Implemented 32 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 483 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings
    Info: Processing ended: Thu Oct 14 17:17:01 2004
    Info: Elapsed time: 00:00:10