pan.ptf

VERILOG HDL 实际工控项目源码

SYSTEM pan
{
   System_Wizard_Version = "4.10";
   System_Wizard_Build = "208";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "FLEX10K";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "1";
      do_build_sim = "1";
      board_class = "";
      hdl_language = "verilog";
      view_master_columns = "0";
      view_master_priorities = "0";
      device_family_id = "STRATIXII";
      name_column_width = "75";
      desc_column_width = "75";
      bustype_column_width = "0";
      base_column_width = "75";
      end_column_width = "75";
      view_frame_window = "102:96:819:576";
   }
   MODULE avalon_ahb_bridge_0
   {
      class = "altera_avalon_avalon_ahb_bridge";
      class_version = "2.0";
      MASTER ahb_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "AHB";
            Bridges_To = "avalon_slave";
            Has_Base_Address = "1";
            Is_Base_Editable = "0";
            Address_Width = "0";
            #This is filled in by SoPC Builder
            Data_Width = "32";
            Base_Address = "--unknown--";
            Has_IRQ = "0";
            IRQ = "N/A";
         }
      }
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "ahb_master";
            Has_Base_Address = "1";
            Is_Base_Editable = "0";
            Address_Width = "0";
            #This is filled in by SoPC Builder
            Address_Alignment = "dynamic";
            Data_Width = "32";
            Base_Address = "--unknown--";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         View 
         {
            Is_Collapsed = "0";
            MESSAGES 
            {
            }
         }
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL a
            {
               name = "  ahb_master";
               format = "Divider";
            }
            #SIGNAL b { name = "hsel";                                       }
            SIGNAL c
            {
               name = "hready";
            }
            #SIGNAL d { name = "hreadyi";                                    }
            SIGNAL e
            {
               name = "haddr";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "hwdata";
               radix = "hexadecimal";
            }
            SIGNAL g
            {
               name = "hrdata";
               radix = "hexadecimal";
            }
            SIGNAL h
            {
               name = "hwrite";
            }
            SIGNAL i
            {
               name = "hsize";
               radix = "unsigned";
            }
            #SIGNAL j { name = "hburst_code";        format = "Literal";     }
            SIGNAL k
            {
               name = "htrans_code";
               format = "Literal";
            }
            SIGNAL l
            {
               name = "hresp_code";
               format = "Literal";
            }
            SIGNAL m
            {
               name = "  avalon_slave";
               format = "Divider";
            }
            SIGNAL m2
            {
               name = "chipselect";
            }
            SIGNAL n
            {
               name = "address";
               radix = "hexadecimal";
            }
            SIGNAL o
            {
               name = "byteenable";
            }
            SIGNAL p
            {
               name = "write";
            }
            SIGNAL r
            {
               name = "writedata";
               radix = "hexadecimal";
            }
            SIGNAL s
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL t
            {
               name = "waitrequest";
            }
         }
         MODELSIM 
         {
            SETUP_COMMANDS 
            {
               #hburst_vfn = "virtual function { (hburst_types) __MODULE_PATH__/__FIX_ME_UP__/hburst } hburst_code";
               htrans_vfn = "virtual function { (htrans_types) __MODULE_PATH__/__FIX_ME_UP__/htrans } htrans_code";
               hresp_vfn = "virtual function { (hresp_types) __MODULE_PATH__/__FIX_ME_UP__/hresp } hresp_code";
            }
            TYPES 
            {
               type1 = "virtual type { IDLE BUSY NONSEQ SEQ } htrans_types";
               #type2 = "virtual type { SINGLE INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 } hburst_types";
               type3 = "virtual type { OKAY ERROR RETRY SPLIT } hresp_types";
            }
         }
      }
   }
}