addr_code.v

VERILOG HDL 实际工控项目源码

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
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// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
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// limited to  modification,  reverse engineering,  de-compiling, or use  with
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// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
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// Generated by Quartus II Version 4.1 (Build Build 207 08/26/2004)
// Created on Wed Sep 08 20:44:56 2004

//  Module Declaration
module addr_code
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	mcu_a, mcu_rd, mcu_wr, strb, page, rd_clk, g_clk, rd_add, dsp_sram_ce, 
	dsp_sram_oe, dsp_sram_we, dsp_flash_ce, dsp_flash_oe, dsp_flash_we, bus1_ce, 
	bus1_dir, bus2_ce, bus2_dir, can_cs, addr_cs, dsp_tck0, dsp_tck1, dsp_run, 
	dsp_dram_ce, dsp_dram_oe, dsp_dram_rw, mcu_dram_ce
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [15:12] mcu_a;
	input mcu_rd;
	input mcu_wr;
	input strb;
	input [3:0] page;
	input rd_clk;
	input g_clk;
	input [15:12] rd_add;
	output dsp_sram_ce;
	output dsp_sram_oe;
	output dsp_sram_we;
	output dsp_flash_ce;
	output dsp_flash_oe;
	output dsp_flash_we;
	output bus1_ce;
	output bus1_dir;
	output bus2_ce;
	output bus2_dir;
	output can_cs;
	output addr_cs;
	output dsp_tck0;
	output dsp_tck1;
	output dsp_run;
	output dsp_dram_ce;
	output dsp_dram_oe;
	output dsp_dram_rw;
	output mcu_dram_ce;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
wire mcu_rw;
assign mcu_rw=mcu_rd&mcu_wr;


assign dsp_sram_ce=strb|page[3];//改为page[0]
assign dsp_sram_oe=(~rd_clk)|strb;
assign dsp_sram_we=rd_clk|strb;

assign dsp_flash_ce=strb|page[1];
assign dsp_flash_oe=(~rd_clk)|strb;
assign dsp_flash_we=rd_clk|strb;


//assign dsp_rdy=~dram_busy;
assign bus1_ce=strb|page[2];

assign bus1_dir=~rd_clk;
assign bus2_ce=0;
assign bus2_dir=0;

assign dsp_dram_ce=strb|page[2]|(~rd_add[15])|rd_add[14]|(~rd_add[13])|rd_add[12];
assign dsp_dram_oe=strb|(~rd_clk);
assign dsp_dram_rw=strb|rd_clk;

assign mcu_dram_ce=(~mcu_a[15])|mcu_a[14]|mcu_a[13]|mcu_a[12];//8000h
assign can_cs= mcu_rw|(~mcu_a[15])|mcu_a[14]|mcu_a[13]|(~mcu_a[12]);//9000h
assign addr_cs=mcu_rd|(~mcu_a[15])|mcu_a[14]|(~mcu_a[13])|mcu_a[12];//a000h
assign dsp_tck0=1;
assign dsp_tck1=1;

wire wr_led;
assign wr_led=strb|page[2]|(~rd_add[15])|(~rd_add[14])|rd_add[13]|rd_add[12];
reg dsp_run;

always @(negedge wr_led)
begin
	dsp_run<=~dsp_run;	
end


endmodule