myfifo.map.qmsg

VERILOG HDL 实际工控项目源码

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 14 mydram.v(87) " "Warning: Verilog HDL expression warning at mydram.v(87): truncated operand with size 16 to match size of smaller operand (14)" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 87 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "ad_collect:inst1\|int_reg\[0\]~55 11 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: ad_collect:inst1\|int_reg\[0\]~55" {  } { { "E:/FPGApro/ad_collect.v" "" "int_reg\[0\]~55" { Text "E:/FPGApro/ad_collect.v" 187 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "d:/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "d:/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "d:/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "d:/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_PREPROCESS_STAT" "\|myfifo\|watchdog:inst\|step 4 0 " "Info: State machine \|myfifo\|watchdog:inst\|step contains 4 states and 0 state bits" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_PREPROCESS_STAT" "\|myfifo\|ad_collect:inst1\|step 9 0 " "Info: State machine \|myfifo\|ad_collect:inst1\|step contains 9 states and 0 state bits" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|myfifo\|watchdog:inst\|step " "Info: Selected Auto state machine encoding method for state machine \|myfifo\|watchdog:inst\|step" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|myfifo\|watchdog:inst\|step " "Info: Encoding result for state machine \|myfifo\|watchdog:inst\|step" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "watchdog:inst\|step~21 " "Info: Encoded state bit watchdog:inst\|step~21" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "watchdog:inst\|step~20 " "Info: Encoded state bit watchdog:inst\|step~20" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "watchdog:inst\|step~19 " "Info: Encoded state bit watchdog:inst\|step~19" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "watchdog:inst\|step~18 " "Info: Encoded state bit watchdog:inst\|step~18" {  } {  } 0}  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|watchdog:inst\|step.00 0000 " "Info: State \|myfifo\|watchdog:inst\|step.00 uses code string 0000" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 56 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|watchdog:inst\|step.10 0011 " "Info: State \|myfifo\|watchdog:inst\|step.10 uses code string 0011" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 56 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|watchdog:inst\|step.01 0101 " "Info: State \|myfifo\|watchdog:inst\|step.01 uses code string 0101" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 56 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|watchdog:inst\|step.11 1001 " "Info: State \|myfifo\|watchdog:inst\|step.11 uses code string 1001" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 56 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|myfifo\|ad_collect:inst1\|step " "Info: Selected Auto state machine encoding method for state machine \|myfifo\|ad_collect:inst1\|step" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|myfifo\|ad_collect:inst1\|step " "Info: Encoding result for state machine \|myfifo\|ad_collect:inst1\|step" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "9 " "Info: Completed encoding using 9 state bits" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~67 " "Info: Encoded state bit ad_collect:inst1\|step~67" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~66 " "Info: Encoded state bit ad_collect:inst1\|step~66" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~65 " "Info: Encoded state bit ad_collect:inst1\|step~65" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~64 " "Info: Encoded state bit ad_collect:inst1\|step~64" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~63 " "Info: Encoded state bit ad_collect:inst1\|step~63" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~62 " "Info: Encoded state bit ad_collect:inst1\|step~62" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~61 " "Info: Encoded state bit ad_collect:inst1\|step~61" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~60 " "Info: Encoded state bit ad_collect:inst1\|step~60" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad_collect:inst1\|step~59 " "Info: Encoded state bit ad_collect:inst1\|step~59" {  } {  } 0}  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0000 000000000 " "Info: State \|myfifo\|ad_collect:inst1\|step.0000 uses code string 000000000" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0111 000000110 " "Info: State \|myfifo\|ad_collect:inst1\|step.0111 uses code string 000000110" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0110 000001010 " "Info: State \|myfifo\|ad_collect:inst1\|step.0110 uses code string 000001010" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0101 000010010 " "Info: State \|myfifo\|ad_collect:inst1\|step.0101 uses code string 000010010" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0100 000100010 " "Info: State \|myfifo\|ad_collect:inst1\|step.0100 uses code string 000100010" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0011 001000010 " "Info: State \|myfifo\|ad_collect:inst1\|step.0011 uses code string 001000010" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0010 010000010 " "Info: State \|myfifo\|ad_collect:inst1\|step.0010 uses code string 010000010" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.0001 100000010 " "Info: State \|myfifo\|ad_collect:inst1\|step.0001 uses code string 100000010" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myfifo\|ad_collect:inst1\|step.1000 000000011 " "Info: State \|myfifo\|ad_collect:inst1\|step.1000 uses code string 000000011" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 57 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ad_wr VCC " "Warning: Pin ad_wr stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -40 448 624 -24 "ad_wr" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ad_sel GND " "Warning: Pin ad_sel stuck at GND" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -8 448 624 8 "ad_sel" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "bus2_dir GND " "Warning: Pin bus2_dir stuck at GND" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -328 424 600 -312 "bus2_dir" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dsp_tck0 VCC " "Warning: Pin dsp_tck0 stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -232 424 600 -216 "dsp_tck0" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dsp_tck1 VCC " "Warning: Pin dsp_tck1 stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -216 424 600 -200 "dsp_tck1" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "bus2_ce GND " "Warning: Pin bus2_ce stuck at GND" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -344 424 600 -328 "bus2_ce" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ad_sl\[3\] VCC " "Warning: Pin ad_sl\[3\] stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -72 448 624 -56 "ad_sl\[3..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ad_sl\[2\] VCC " "Warning: Pin ad_sl\[2\] stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -72 448 624 -56 "ad_sl\[3..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ad_sl\[1\] VCC " "Warning: Pin ad_sl\[1\] stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -72 448 624 -56 "ad_sl\[3..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ad_sl\[0\] VCC " "Warning: Pin ad_sl\[0\] stuck at VCC" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -72 448 624 -56 "ad_sl\[3..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 45 -1 0 } } { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 46 -1 0 } } { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 48 -1 0 } } { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 51 -1 0 } }  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "6 " "Warning: Design contains 6 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "page\[0\] " "Warning: No output dependent on input pin page\[0\]" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 376 -32 136 392 "page\[3..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "ad_busy " "Warning: No output dependent on input pin ad_busy" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 8 -40 128 24 "ad_busy" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "rd_addr\[7\] " "Warning: No output dependent on input pin rd_addr\[7\]" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 296 -32 136 312 "rd_addr\[7..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "rd_addr\[6\] " "Warning: No output dependent on input pin rd_addr\[6\]" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 296 -32 136 312 "rd_addr\[7..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "rd_addr\[5\] " "Warning: No output dependent on input pin rd_addr\[5\]" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 296 -32 136 312 "rd_addr\[7..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "rd_addr\[4\] " "Warning: No output dependent on input pin rd_addr\[4\]" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 296 -32 136 312 "rd_addr\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "574 " "Info: Implemented 574 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "43 " "Info: Implemented 43 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "483 " "Info: Implemented 483 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 31 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 14 17:17:01 2004 " "Info: Processing ended: Thu Oct 14 17:17:01 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}