myfifo.map.qmsg

VERILOG HDL 实际工控项目源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 14 17:16:51 2004 " "Info: Processing started: Thu Oct 14 17:16:51 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off myfifo -c myfifo " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off myfifo -c myfifo" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myfifo.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file myfifo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 myfifo " "Info: Found entity 1: myfifo" {  } { { "E:/FPGApro/myfifo.bdf" "myfifo" "" { Schematic "E:/FPGApro/myfifo.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mydram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mydram.v" { { "Info" "ISGN_ENTITY_NAME" "1 mydram " "Info: Found entity 1: mydram" {  } { { "E:/FPGApro/mydram.v" "mydram" "" { Text "E:/FPGApro/mydram.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "wram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file wram.v" { { "Info" "ISGN_ENTITY_NAME" "1 wram " "Info: Found entity 1: wram" {  } { { "E:/FPGApro/wram.v" "wram" "" { Text "E:/FPGApro/wram.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watchdog.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file watchdog.v" { { "Info" "ISGN_ENTITY_NAME" "1 watchdog " "Info: Found entity 1: watchdog" {  } { { "E:/FPGApro/watchdog.v" "watchdog" "" { Text "E:/FPGApro/watchdog.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad_collect.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad_collect.v" { { "Info" "ISGN_ENTITY_NAME" "1 ad_collect " "Info: Found entity 1: ad_collect" {  } { { "E:/FPGApro/ad_collect.v" "ad_collect" "" { Text "E:/FPGApro/ad_collect.v" 31 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addr_code.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file addr_code.v" { { "Info" "ISGN_ENTITY_NAME" "1 addr_code " "Info: Found entity 1: addr_code" {  } { { "E:/FPGApro/addr_code.v" "addr_code" "" { Text "E:/FPGApro/addr_code.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "13 12 ad_collect.v(139) " "Warning: Verilog HDL expression warning at ad_collect.v(139): truncated operand with size 13 to match size of smaller operand (12)" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 3 ad_collect.v(159) " "Warning: Verilog HDL expression warning at ad_collect.v(159): truncated operand with size 4 to match size of smaller operand (3)" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 159 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 ad_collect.v(167) " "Warning: Verilog HDL expression warning at ad_collect.v(167): truncated operand with size 3 to match size of smaller operand (2)" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 167 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ad_sel ad_collect.v(85) " "Warning: Verilog HDL Always Construct warning at ad_collect.v(85): variable ad_sel may not be assigned a new value in every possible path through the Always Construct.  Variable ad_sel holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ad_sl ad_collect.v(85) " "Warning: Verilog HDL Always Construct warning at ad_collect.v(85): variable ad_sl may not be assigned a new value in every possible path through the Always Construct.  Variable ad_sl holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "ad_wr ad_collect.v(85) " "Warning: Verilog HDL Always Construct warning at ad_collect.v(85): variable ad_wr may not be assigned a new value in every possible path through the Always Construct.  Variable ad_wr holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 ad_collect.v(193) " "Warning: Verilog HDL expression warning at ad_collect.v(193): truncated operand with size 12 to match size of smaller operand (11)" {  } { { "E:/FPGApro/ad_collect.v" "" "" { Text "E:/FPGApro/ad_collect.v" 193 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "27 26 watchdog.v(99) " "Warning: Verilog HDL expression warning at watchdog.v(99): truncated operand with size 27 to match size of smaller operand (26)" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "27 26 watchdog.v(114) " "Warning: Verilog HDL expression warning at watchdog.v(114): truncated operand with size 27 to match size of smaller operand (26)" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "rd_addr mydram.v(78) " "Warning: Verilog HDL Always Construct warning at mydram.v(78): variable rd_addr is used in Always Construct, but isn't in the Always Construct's Event Control" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "coll_mem mydram.v(78) " "Warning: Verilog HDL Always Construct warning at mydram.v(78): variable coll_mem is used in Always Construct, but isn't in the Always Construct's Event Control" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "d_out mydram.v(75) " "Warning: Verilog HDL Always Construct warning at mydram.v(75): variable d_out may not be assigned a new value in every possible path through the Always Construct.  Variable d_out holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 75 0 0 } }  } 0}