myfifo.hier_info

VERILOG HDL 实际工控项目源码

|myfifo
full_int <= ad_collect:inst1.full_int
rd_clk => watchdog:inst.rd_clk
rd_clk => addr_code:inst5.rd_clk
rd_clk => mydram:inst2.rd_clk
g_clk => watchdog:inst.g_clk
g_clk => ad_collect:inst1.g_clk
g_clk => addr_code:inst5.g_clk
g_clk => mydram:inst2.g_clk
dog_en => watchdog:inst.dog_en
strb => watchdog:inst.strb
strb => addr_code:inst5.strb
strb => mydram:inst2.strb
page[0] => watchdog:inst.page[0]
page[0] => addr_code:inst5.page[0]
page[0] => mydram:inst2.page[0]
page[1] => watchdog:inst.page[1]
page[1] => addr_code:inst5.page[1]
page[1] => mydram:inst2.page[1]
page[2] => watchdog:inst.page[2]
page[2] => addr_code:inst5.page[2]
page[2] => mydram:inst2.page[2]
page[3] => watchdog:inst.page[3]
page[3] => addr_code:inst5.page[3]
page[3] => mydram:inst2.page[3]
rd_add[12] => watchdog:inst.rd_add[12]
rd_add[12] => addr_code:inst5.rd_add[12]
rd_add[12] => mydram:inst2.rd_add[12]
rd_add[13] => watchdog:inst.rd_add[13]
rd_add[13] => addr_code:inst5.rd_add[13]
rd_add[13] => mydram:inst2.rd_add[13]
rd_add[14] => watchdog:inst.rd_add[14]
rd_add[14] => addr_code:inst5.rd_add[14]
rd_add[14] => mydram:inst2.rd_add[14]
rd_add[15] => watchdog:inst.rd_add[15]
rd_add[15] => addr_code:inst5.rd_add[15]
rd_add[15] => mydram:inst2.rd_add[15]
ad_busy => ad_collect:inst1.ad_busy
ad_eoc => ad_collect:inst1.ad_eoc
ad_cs <= ad_collect:inst1.ad_cs
ad_wr <= ad_collect:inst1.ad_wr
ad_rd <= ad_collect:inst1.ad_rd
ad_sel <= ad_collect:inst1.ad_sel
ad_conv <= ad_collect:inst1.ad_conv
dsp_sram_ce <= addr_code:inst5.dsp_sram_ce
mcu_rd => addr_code:inst5.mcu_rd
mcu_wr => addr_code:inst5.mcu_wr
mcu_a[12] => addr_code:inst5.mcu_a[12]
mcu_a[13] => addr_code:inst5.mcu_a[13]
mcu_a[14] => addr_code:inst5.mcu_a[14]
mcu_a[15] => addr_code:inst5.mcu_a[15]
dsp_sram_oe <= addr_code:inst5.dsp_sram_oe
dsp_sram_we <= addr_code:inst5.dsp_sram_we
dsp_flash_ce <= addr_code:inst5.dsp_flash_ce
dsp_flash_oe <= addr_code:inst5.dsp_flash_oe
dsp_flash_we <= addr_code:inst5.dsp_flash_we
bus1_ce <= addr_code:inst5.bus1_ce
bus1_dir <= addr_code:inst5.bus1_dir
bus2_dir <= addr_code:inst5.bus2_dir
can_cs <= addr_code:inst5.can_cs
addr_cs <= addr_code:inst5.addr_cs
dsp_tck0 <= addr_code:inst5.dsp_tck0
dsp_tck1 <= addr_code:inst5.dsp_tck1
dsp_run <= addr_code:inst5.dsp_run
bus2_ce <= addr_code:inst5.bus2_ce
dsp_rdy <= mydram:inst2.dsp_rdy
dram_busy => mydram:inst2.dram_busy
ad_db[0] => mydram:inst2.ad_db[0]
ad_db[1] => mydram:inst2.ad_db[1]
ad_db[2] => mydram:inst2.ad_db[2]
ad_db[3] => mydram:inst2.ad_db[3]
ad_db[4] => mydram:inst2.ad_db[4]
ad_db[5] => mydram:inst2.ad_db[5]
ad_db[6] => mydram:inst2.ad_db[6]
ad_db[7] => mydram:inst2.ad_db[7]
ad_db[8] => mydram:inst2.ad_db[8]
ad_db[9] => mydram:inst2.ad_db[9]
ad_db[10] => mydram:inst2.ad_db[10]
ad_db[11] => mydram:inst2.ad_db[11]
ad_db[12] => mydram:inst2.ad_db[12]
ad_db[13] => mydram:inst2.ad_db[13]
d[0] <= mydram:inst2.d[0]
d[1] <= mydram:inst2.d[1]
d[2] <= mydram:inst2.d[2]
d[3] <= mydram:inst2.d[3]
d[4] <= mydram:inst2.d[4]
d[5] <= mydram:inst2.d[5]
d[6] <= mydram:inst2.d[6]
d[7] <= mydram:inst2.d[7]
d[8] <= mydram:inst2.d[8]
d[9] <= mydram:inst2.d[9]
d[10] <= mydram:inst2.d[10]
d[11] <= mydram:inst2.d[11]
d[12] <= mydram:inst2.d[12]
d[13] <= mydram:inst2.d[13]
d[14] <= mydram:inst2.d[14]
d[15] <= mydram:inst2.d[15]
rd_addr[0] => mydram:inst2.rd_addr[0]
rd_addr[1] => mydram:inst2.rd_addr[1]
rd_addr[2] => mydram:inst2.rd_addr[2]
rd_addr[3] => mydram:inst2.rd_addr[3]
rd_addr[4] => mydram:inst2.rd_addr[4]
rd_addr[5] => mydram:inst2.rd_addr[5]
rd_addr[6] => mydram:inst2.rd_addr[6]
rd_addr[7] => mydram:inst2.rd_addr[7]
dsp_rst <= watchdog:inst.dsp_rst
dsp_dram_ce <= addr_code:inst5.dsp_dram_ce
dsp_dram_oe <= addr_code:inst5.dsp_dram_oe
dsp_dram_rw <= addr_code:inst5.dsp_dram_rw
mcu_dram_ce <= addr_code:inst5.mcu_dram_ce
dir_4052 <= watchdog:inst.dir_4052
ad_sl[0] <= ad_collect:inst1.ad_sl[0]
ad_sl[1] <= ad_collect:inst1.ad_sl[1]
ad_sl[2] <= ad_collect:inst1.ad_sl[2]
ad_sl[3] <= ad_collect:inst1.ad_sl[3]


|myfifo|ad_collect:inst1
rst => eoc_reg[0].ACLR
rst => collect_reg[1].ACLR
rst => collect_reg[0].ACLR
rst => ad_rd~reg0.PRESET
rst => ad_cs~reg0.PRESET
rst => wr_addr[2]~reg0.ACLR
rst => wr_addr[1]~reg0.ACLR
rst => wr_addr[0]~reg0.ACLR
rst => ad_conv~reg0.PRESET
rst => change_end.ACLR
rst => counter[1].ACLR
rst => counter[0].ACLR
rst => delay[11].ACLR
rst => delay[10].ACLR
rst => delay[9].ACLR
rst => delay[8].ACLR
rst => delay[7].ACLR
rst => delay[6].ACLR
rst => delay[5].ACLR
rst => delay[4].ACLR
rst => delay[3].ACLR
rst => delay[2].ACLR
rst => delay[1].ACLR
rst => delay[0].ACLR
rst => int_reg[10].ACLR
rst => int_reg[9].ACLR
rst => int_reg[8].ACLR
rst => int_reg[7].ACLR
rst => int_reg[6].ACLR
rst => int_reg[5].ACLR
rst => int_reg[4].ACLR
rst => int_reg[3].ACLR
rst => int_reg[2].ACLR
rst => int_reg[1].ACLR
rst => int_reg[0].ACLR
rst => full_int~reg0.PRESET
rst => eoc_reg[1].ACLR
rst => ad_sel$latch.LATCH_ENABLE
rst => ad_wr$latch.LATCH_ENABLE
rst => step~28.IN1
g_clk => eoc_reg[0].CLK
g_clk => collect_reg[1].CLK
g_clk => collect_reg[0].CLK
g_clk => ad_rd~reg0.CLK
g_clk => ad_cs~reg0.CLK
g_clk => wr_addr[2]~reg0.CLK
g_clk => wr_addr[1]~reg0.CLK
g_clk => wr_addr[0]~reg0.CLK
g_clk => ad_conv~reg0.CLK
g_clk => change_end.CLK
g_clk => counter[1].CLK
g_clk => counter[0].CLK
g_clk => delay[11].CLK
g_clk => delay[10].CLK
g_clk => delay[9].CLK
g_clk => delay[8].CLK
g_clk => delay[7].CLK
g_clk => delay[6].CLK
g_clk => delay[5].CLK
g_clk => delay[4].CLK
g_clk => delay[3].CLK
g_clk => delay[2].CLK
g_clk => delay[1].CLK
g_clk => delay[0].CLK
g_clk => int_reg[10].CLK
g_clk => int_reg[9].CLK
g_clk => int_reg[8].CLK
g_clk => int_reg[7].CLK
g_clk => int_reg[6].CLK
g_clk => int_reg[5].CLK
g_clk => int_reg[4].CLK
g_clk => int_reg[3].CLK
g_clk => int_reg[2].CLK
g_clk => int_reg[1].CLK
g_clk => int_reg[0].CLK
g_clk => full_int~reg0.CLK
g_clk => eoc_reg[1].CLK
g_clk => step~27.IN1
ad_busy => ~NO_FANOUT~
ad_eoc => eoc_reg[0].DATAIN
full_int <= full_int~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_cs <= ad_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_sel <= ad_sel$latch.DB_MAX_OUTPUT_PORT_TYPE
ad_rd <= ad_rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_wr <= ad_wr$latch.DB_MAX_OUTPUT_PORT_TYPE
ad_sl[0] <= ad_wr$latch.DB_MAX_OUTPUT_PORT_TYPE
ad_sl[1] <= ad_wr$latch.DB_MAX_OUTPUT_PORT_TYPE
ad_sl[2] <= ad_wr$latch.DB_MAX_OUTPUT_PORT_TYPE
ad_sl[3] <= ad_wr$latch.DB_MAX_OUTPUT_PORT_TYPE
ad_conv <= ad_conv~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_addr[0] <= wr_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_addr[1] <= wr_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_addr[2] <= wr_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|myfifo|watchdog:inst
page[0] => ~NO_FANOUT~
page[1] => ~NO_FANOUT~
page[2] => feed_dog~0.IN0
page[3] => ~NO_FANOUT~
rd_add[12] => feed_dog.IN0
rd_add[13] => feed_dog~3.IN1
rd_add[14] => feed_dog~2.IN1
rd_add[15] => feed_dog~1.IN1
rd_clk => ~NO_FANOUT~
g_clk => dog_reg[0].CLK
g_clk => rst~reg0.CLK
g_clk => watch_reg[25].CLK
g_clk => watch_reg[24].CLK
g_clk => watch_reg[23].CLK
g_clk => watch_reg[22].CLK
g_clk => watch_reg[21].CLK
g_clk => watch_reg[20].CLK
g_clk => watch_reg[19].CLK
g_clk => watch_reg[18].CLK
g_clk => watch_reg[17].CLK
g_clk => watch_reg[16].CLK
g_clk => watch_reg[15].CLK
g_clk => watch_reg[14].CLK
g_clk => watch_reg[13].CLK
g_clk => watch_reg[12].CLK
g_clk => watch_reg[11].CLK
g_clk => watch_reg[10].CLK
g_clk => watch_reg[9].CLK
g_clk => watch_reg[8].CLK
g_clk => watch_reg[7].CLK
g_clk => watch_reg[6].CLK
g_clk => watch_reg[5].CLK
g_clk => watch_reg[4].CLK
g_clk => watch_reg[3].CLK
g_clk => watch_reg[2].CLK
g_clk => watch_reg[1].CLK
g_clk => watch_reg[0].CLK
g_clk => dog_reg[1].CLK
g_clk => step~5.IN1
dog_en => dog_reg~0.OUTPUTSELECT
dog_en => dog_reg~1.OUTPUTSELECT
strb => feed_dog~0.IN1
dsp_rst <= rst~reg0.DB_MAX_OUTPUT_PORT_TYPE
rst <= rst~reg0.DB_MAX_OUTPUT_PORT_TYPE
dir_4052 <= dog_clk.DB_MAX_OUTPUT_PORT_TYPE


|myfifo|addr_code:inst5
mcu_a[12] => mcu_dram_ce~2.IN0
mcu_a[12] => addr_cs~3.IN0
mcu_a[12] => can_cs~3.IN1
mcu_a[13] => mcu_dram_ce~1.IN0
mcu_a[13] => can_cs~2.IN0
mcu_a[13] => addr_cs~2.IN0
mcu_a[14] => mcu_dram_ce~0.IN0
mcu_a[14] => can_cs~1.IN0
mcu_a[14] => addr_cs~1.IN0
mcu_a[15] => can_cs~0.IN1
mcu_a[15] => addr_cs~0.IN1
mcu_a[15] => mcu_dram_ce~0.IN1
mcu_rd => mcu_rw.IN0
mcu_rd => addr_cs~0.IN0
mcu_wr => mcu_rw.IN1
strb => dsp_sram_ce~0.IN0
strb => dsp_sram_oe~0.IN0
strb => dsp_sram_we~0.IN0
strb => dsp_flash_ce~0.IN0
strb => bus1_ce~0.IN0
strb => dsp_dram_oe~0.IN0
page[0] => ~NO_FANOUT~
page[1] => dsp_flash_ce~0.IN1
page[2] => bus1_ce~0.IN1
page[3] => dsp_sram_ce~0.IN1
rd_clk => dsp_sram_we~0.IN1
rd_clk => dsp_sram_oe~0.IN1
rd_clk => dsp_dram_oe~0.IN1
rd_clk => bus1_dir.DATAIN
g_clk => ~NO_FANOUT~
rd_add[12] => dsp_dram_ce~2.IN0
rd_add[12] => wr_led.IN0
rd_add[13] => wr_led~2.IN0
rd_add[13] => dsp_dram_ce~1.IN0
rd_add[14] => dsp_dram_ce~0.IN1
rd_add[14] => wr_led~1.IN1
rd_add[15] => wr_led~0.IN1
dsp_sram_ce <= dsp_sram_ce~0.DB_MAX_OUTPUT_PORT_TYPE
dsp_sram_oe <= dsp_sram_oe~0.DB_MAX_OUTPUT_PORT_TYPE
dsp_sram_we <= dsp_sram_we~0.DB_MAX_OUTPUT_PORT_TYPE
dsp_flash_ce <= dsp_flash_ce~0.DB_MAX_OUTPUT_PORT_TYPE
dsp_flash_oe <= dsp_sram_oe~0.DB_MAX_OUTPUT_PORT_TYPE
dsp_flash_we <= dsp_sram_we~0.DB_MAX_OUTPUT_PORT_TYPE
bus1_ce <= bus1_ce~0.DB_MAX_OUTPUT_PORT_TYPE
bus1_dir <= rd_clk.DB_MAX_OUTPUT_PORT_TYPE
bus2_ce <= <GND>
bus2_dir <= <GND>
can_cs <= can_cs~3.DB_MAX_OUTPUT_PORT_TYPE
addr_cs <= addr_cs~3.DB_MAX_OUTPUT_PORT_TYPE
dsp_tck0 <= <VCC>
dsp_tck1 <= <VCC>
dsp_run <= dsp_run~reg0.DB_MAX_OUTPUT_PORT_TYPE
dsp_dram_ce <= dsp_dram_ce~2.DB_MAX_OUTPUT_PORT_TYPE
dsp_dram_oe <= dsp_dram_oe~0.DB_MAX_OUTPUT_PORT_TYPE
dsp_dram_rw <= dsp_sram_we~0.DB_MAX_OUTPUT_PORT_TYPE
mcu_dram_ce <= mcu_dram_ce~2.DB_MAX_OUTPUT_PORT_TYPE


|myfifo|mydram:inst2
rd_clk => rdy_en~0.IN1
rd_clk => rd_en~0.IN1
wr_addr[0] => Decoder~0.IN3
wr_addr[1] => Decoder~0.IN2
wr_addr[2] => Decoder~0.IN1
wr_addr[3] => Decoder~0.IN0
wr_addr[4] => ~NO_FANOUT~
wr_addr[5] => ~NO_FANOUT~
wr_addr[6] => ~NO_FANOUT~
page[0] => ~NO_FANOUT~
page[1] => ~NO_FANOUT~
page[2] => rd_en~1.IN0