myfifo.tan.qmsg

VERILOG HDL 实际工控项目源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "page\[2\] register register watchdog:inst\|dog_clk watchdog:inst\|dog_clk 125.0 MHz Internal " "Info: Clock page\[2\] Internal fmax is restricted to 125.0 MHz between source register watchdog:inst\|dog_clk and destination register watchdog:inst\|dog_clk" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns watchdog:inst\|dog_clk 1 REG LC3_E24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns watchdog:inst\|dog_clk 2 REG LC3_E24 3 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "page\[2\] destination 15.200 ns + Shortest register " "Info: + Shortest clock path from clock page\[2\] to destination register is 15.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns page\[2\] 1 CLK PIN_59 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_59; Fanout = 3; CLK Node = 'page\[2\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { page[2] } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 376 -32 136 392 "page\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 9.500 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 9.500 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "6.000 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.400 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.400 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 15.200 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 15.200 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 53.29 % " "Info: Total cell delay = 8.100 ns ( 53.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 46.71 % " "Info: Total interconnect delay = 7.100 ns ( 46.71 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.200 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "page\[2\] source 15.200 ns - Longest register " "Info: - Longest clock path from clock page\[2\] to source register is 15.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns page\[2\] 1 CLK PIN_59 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_59; Fanout = 3; CLK Node = 'page\[2\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { page[2] } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 376 -32 136 392 "page\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 9.500 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 9.500 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "6.000 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.400 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.400 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 15.200 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 15.200 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 53.29 % " "Info: Total cell delay = 8.100 ns ( 53.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 46.71 % " "Info: Total interconnect delay = 7.100 ns ( 46.71 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.200 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.200 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.200 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.200 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.200 ns" { page[2] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "rd_add\[12\] register register watchdog:inst\|dog_clk watchdog:inst\|dog_clk 125.0 MHz Internal " "Info: Clock rd_add\[12\] Internal fmax is restricted to 125.0 MHz between source register watchdog:inst\|dog_clk and destination register watchdog:inst\|dog_clk" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns watchdog:inst\|dog_clk 1 REG LC3_E24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns watchdog:inst\|dog_clk 2 REG LC3_E24 3 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_add\[12\] destination 15.100 ns + Shortest register " "Info: + Shortest clock path from clock rd_add\[12\] to destination register is 15.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns rd_add\[12\] 1 CLK PIN_67 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_67; Fanout = 2; CLK Node = 'rd_add\[12\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { rd_add[12] } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.300 ns) 9.400 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(3.600 ns) + CELL(2.300 ns) = 9.400 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.900 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.300 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.300 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 15.100 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 15.100 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 53.64 % " "Info: Total cell delay = 8.100 ns ( 53.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 46.36 % " "Info: Total interconnect delay = 7.000 ns ( 46.36 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.100 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_add\[12\] source 15.100 ns - Longest register " "Info: - Longest clock path from clock rd_add\[12\] to source register is 15.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns rd_add\[12\] 1 CLK PIN_67 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_67; Fanout = 2; CLK Node = 'rd_add\[12\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { rd_add[12] } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.300 ns) 9.400 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(3.600 ns) + CELL(2.300 ns) = 9.400 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.900 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.300 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.300 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 15.100 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 15.100 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 53.64 % " "Info: Total cell delay = 8.100 ns ( 53.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 46.36 % " "Info: Total interconnect delay = 7.000 ns ( 46.36 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.100 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.100 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.100 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.100 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.100 ns" { rd_add[12] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "rd_add\[15\] register register watchdog:inst\|dog_clk watchdog:inst\|dog_clk 125.0 MHz Internal " "Info: Clock rd_add\[15\] Internal fmax is restricted to 125.0 MHz between source register watchdog:inst\|dog_clk and destination register watchdog:inst\|dog_clk" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns watchdog:inst\|dog_clk 1 REG LC3_E24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns watchdog:inst\|dog_clk 2 REG LC3_E24 3 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_add\[15\] destination 14.600 ns + Shortest register " "Info: + Shortest clock path from clock rd_add\[15\] to destination register is 14.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns rd_add\[15\] 1 CLK PIN_63 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_63; Fanout = 2; CLK Node = 'rd_add\[15\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { rd_add[15] } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.800 ns) 8.900 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(3.600 ns) + CELL(1.800 ns) = 8.900 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.400 ns" { rd_add[15] addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 11.800 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 11.800 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 14.600 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 14.600 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns 52.05 % " "Info: Total cell delay = 7.600 ns ( 52.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 47.95 % " "Info: Total interconnect delay = 7.000 ns ( 47.95 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "14.600 ns" { rd_add[15] addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rd_add\[15\] source 14.600 ns - Longest register " "Info: - Longest clock path from clock rd_add\[15\] to source register is 14.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns rd_add\[15\] 1 CLK PIN_63 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_63; Fanout = 2; CLK Node = 'rd_add\[15\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfif