myfifo.tan.qmsg

VERILOG HDL 实际工控项目源码

{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[4\]~2445 " "Info: Node mydram:inst2\|d_out\[4\]~2445" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[4\]~2431 " "Info: Node mydram:inst2\|d_out\[4\]~2431" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[4\]~2412 " "Info: Node mydram:inst2\|d_out\[4\]~2412" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "g_clk " "Info: Assuming node g_clk is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 480 -32 136 496 "g_clk" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "g_clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "strb " "Info: Assuming node strb is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -360 -32 136 -344 "strb" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "strb" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rd_clk " "Info: Assuming node rd_clk is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 336 -32 136 352 "rd_clk" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rd_clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "page\[2\] " "Info: Assuming node page\[2\] is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 376 -32 136 392 "page\[3..0\]" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "page\[2\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rd_add\[12\] " "Info: Assuming node rd_add\[12\] is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rd_add\[12\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rd_add\[15\] " "Info: Assuming node rd_add\[15\] is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rd_add\[15\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rd_add\[13\] " "Info: Assuming node rd_add\[13\] is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rd_add\[13\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rd_add\[14\] " "Info: Assuming node rd_add\[14\] is an undefined clock" {  } { { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 136 -32 136 152 "rd_add\[15..12\]" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "rd_add\[14\]" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "mydram:inst2\|rd_en~42 " "Info: Detected gated clock mydram:inst2\|rd_en~42 as buffer" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 55 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "mydram:inst2\|rd_en~42" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "mydram:inst2\|rdy_en " "Info: Detected gated clock mydram:inst2\|rdy_en as buffer" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 55 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "mydram:inst2\|rdy_en" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "watchdog:inst\|feed_dog " "Info: Detected gated clock watchdog:inst\|feed_dog as buffer" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "watchdog:inst\|feed_dog" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "addr_code:inst5\|dsp_dram_ce~24 " "Info: Detected gated clock addr_code:inst5\|dsp_dram_ce~24 as buffer" {  } { { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "addr_code:inst5\|dsp_dram_ce~24" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "addr_code:inst5\|wr_led " "Info: Detected gated clock addr_code:inst5\|wr_led as buffer" {  } { { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 101 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "addr_code:inst5\|wr_led" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "g_clk register watchdog:inst\|watch_reg\[9\] register watchdog:inst\|watch_reg\[24\] 33.9 MHz 29.5 ns Internal " "Info: Clock g_clk has Internal fmax of 33.9 MHz between source register watchdog:inst\|watch_reg\[9\] and destination register watchdog:inst\|watch_reg\[24\] (period= 29.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "25.900 ns + Longest register register " "Info: + Longest register to register delay is 25.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns watchdog:inst\|watch_reg\[9\] 1 REG LC4_E15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E15; Fanout = 4; REG Node = 'watchdog:inst\|watch_reg\[9\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|watch_reg[9] } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 119 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns watchdog:inst\|LessThan~398 2 COMB LC1_E15 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_E15; Fanout = 1; COMB Node = 'watchdog:inst\|LessThan~398'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { watchdog:inst|watch_reg[9] watchdog:inst|LessThan~398 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 7.400 ns watchdog:inst\|LessThan~399 3 COMB LC5_E13 1 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 7.400 ns; Loc. = LC5_E13; Fanout = 1; COMB Node = 'watchdog:inst\|LessThan~399'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "4.500 ns" { watchdog:inst|LessThan~398 watchdog:inst|LessThan~399 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 9.800 ns watchdog:inst\|LessThan~400 4 COMB LC6_E13 1 " "Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 9.800 ns; Loc. = LC6_E13; Fanout = 1; COMB Node = 'watchdog:inst\|LessThan~400'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.400 ns" { watchdog:inst|LessThan~399 watchdog:inst|LessThan~400 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 12.200 ns watchdog:inst\|LessThan~403 5 COMB LC4_E13 6 " "Info: 5: + IC(0.600 ns) + CELL(1.800 ns) = 12.200 ns; Loc. = LC4_E13; Fanout = 6; COMB Node = 'watchdog:inst\|LessThan~403'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.400 ns" { watchdog:inst|LessThan~400 watchdog:inst|LessThan~403 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(2.300 ns) 17.000 ns watchdog:inst\|Select~2626 6 COMB LC4_E18 26 " "Info: 6: + IC(2.500 ns) + CELL(2.300 ns) = 17.000 ns; Loc. = LC4_E18; Fanout = 26; COMB Node = 'watchdog:inst\|Select~2626'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "4.800 ns" { watchdog:inst|LessThan~403 watchdog:inst|Select~2626 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.300 ns) 22.400 ns watchdog:inst\|Select~2645 7 COMB LC7_E23 1 " "Info: 7: + IC(3.100 ns) + CELL(2.300 ns) = 22.400 ns; Loc. = LC7_E23; Fanout = 1; COMB Node = 'watchdog:inst\|Select~2645'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.400 ns" { watchdog:inst|Select~2626 watchdog:inst|Select~2645 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.200 ns) 25.900 ns watchdog:inst\|watch_reg\[24\] 8 REG LC2_E13 4 " "Info: 8: + IC(2.300 ns) + CELL(1.200 ns) = 25.900 ns; Loc. = LC2_E13; Fanout = 4; REG Node = 'watchdog:inst\|watch_reg\[24\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "3.500 ns" { watchdog:inst|Select~2645 watchdog:inst|watch_reg[24] } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 119 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 54.05 % " "Info: Total cell delay = 14.000 ns ( 54.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.900 ns 45.95 % " "Info: Total interconnect delay = 11.900 ns ( 45.95 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "25.900 ns" { watchdog:inst|watch_reg[9] watchdog:inst|LessThan~398 watchdog:inst|LessThan~399 watchdog:inst|LessThan~400 watchdog:inst|LessThan~403 watchdog:inst|Select~2626 watchdog:inst|Select~2645 watchdog:inst|watch_reg[24] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock g_clk to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns g_clk 1 CLK PIN_55 211 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 211; CLK Node = 'g_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { g_clk } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 480 -32 136 496 "g_clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns watchdog:inst\|watch_reg\[24\] 2 REG LC2_E13 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_E13; Fanout = 4; REG Node = 'watchdog:inst\|watch_reg\[24\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.500 ns" { g_clk watchdog:inst|watch_reg[24] } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 119 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.300 ns" { g_clk watchdog:inst|watch_reg[24] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock g_clk to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns g_clk 1 CLK PIN_55 211 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 211; CLK Node = 'g_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { g_clk } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { 480 -32 136 496 "g_clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns watchdog:inst\|watch_reg\[9\] 2 REG LC4_E15 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_E15; Fanout = 4; REG Node = 'watchdog:inst\|watch_reg\[9\]'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.500 ns" { g_clk watchdog:inst|watch_reg[9] } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 119 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.300 ns" { g_clk watchdog:inst|watch_reg[9] } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.300 ns" { g_clk watchdog:inst|watch_reg[24] } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.300 ns" { g_clk watchdog:inst|watch_reg[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 119 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 119 -1 0 } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "25.900 ns" { watchdog:inst|watch_reg[9] watchdog:inst|LessThan~398 watchdog:inst|LessThan~399 watchdog:inst|LessThan~400 watchdog:inst|LessThan~403 watchdog:inst|Select~2626 watchdog:inst|Select~2645 watchdog:inst|watch_reg[24] } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.300 ns" { g_clk watchdog:inst|watch_reg[24] } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "5.300 ns" { g_clk watchdog:inst|watch_reg[9] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "strb register register watchdog:inst\|dog_clk watchdog:inst\|dog_clk 125.0 MHz Internal " "Info: Clock strb Internal fmax is restricted to 125.0 MHz between source register watchdog:inst\|dog_clk and destination register watchdog:inst\|dog_clk" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns watchdog:inst\|dog_clk 1 REG LC3_E24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns watchdog:inst\|dog_clk 2 REG LC3_E24 3 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 66.67 % " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 33.33 % " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "strb destination 15.600 ns + Shortest register " "Info: + Shortest clock path from clock strb to destination register is 15.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns strb 1 CLK PIN_47 13 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_47; Fanout = 13; CLK Node = 'strb'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { strb } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -360 -32 136 -344 "strb" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(2.300 ns) 9.900 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(4.100 ns) + CELL(2.300 ns) = 9.900 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "6.400 ns" { strb addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.800 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.800 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 15.600 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 15.600 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 51.92 % " "Info: Total cell delay = 8.100 ns ( 51.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 48.08 % " "Info: Total interconnect delay = 7.500 ns ( 48.08 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.600 ns" { strb addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "strb source 15.600 ns - Longest register " "Info: - Longest clock path from clock strb to source register is 15.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns strb 1 CLK PIN_47 13 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_47; Fanout = 13; CLK Node = 'strb'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { strb } "NODE_NAME" } } } { "E:/FPGApro/myfifo.bdf" "" "" { Schematic "E:/FPGApro/myfifo.bdf" { { -360 -32 136 -344 "strb" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(2.300 ns) 9.900 ns addr_code:inst5\|dsp_dram_ce~24 2 COMB LC2_E6 3 " "Info: 2: + IC(4.100 ns) + CELL(2.300 ns) = 9.900 ns; Loc. = LC2_E6; Fanout = 3; COMB Node = 'addr_code:inst5\|dsp_dram_ce~24'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "6.400 ns" { strb addr_code:inst5|dsp_dram_ce~24 } "NODE_NAME" } } } { "E:/FPGApro/addr_code.v" "" "" { Text "E:/FPGApro/addr_code.v" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.800 ns watchdog:inst\|feed_dog 3 COMB LC7_E6 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.800 ns; Loc. = LC7_E6; Fanout = 1; COMB Node = 'watchdog:inst\|feed_dog'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.900 ns" { addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 15.600 ns watchdog:inst\|dog_clk 4 REG LC3_E24 3 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 15.600 ns; Loc. = LC3_E24; Fanout = 3; REG Node = 'watchdog:inst\|dog_clk'" {  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "2.800 ns" { watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 51.92 % " "Info: Total cell delay = 8.100 ns ( 51.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 48.08 % " "Info: Total interconnect delay = 7.500 ns ( 48.08 % )" {  } {  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.600 ns" { strb addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.600 ns" { strb addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.600 ns" { strb addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "1.800 ns" { watchdog:inst|dog_clk watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.600 ns" { strb addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "15.600 ns" { strb addr_code:inst5|dsp_dram_ce~24 watchdog:inst|feed_dog watchdog:inst|dog_clk } "NODE_NAME" } } }  } 0}  } { { "E:/FPGApro/db/myfifo_cmp.qrpt" "" "" { Report "E:/FPGApro/db/myfifo_cmp.qrpt" Compiler "myfifo" "UNKNOWN" "V1" "E:/FPGApro/db/myfifo.quartus_db" { Floorplan "" "" "" { watchdog:inst|dog_clk } "NODE_NAME" } } } { "E:/FPGApro/watchdog.v" "" "" { Text "E:/FPGApro/watchdog.v" 60 -1 0 } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "rd_clk " "Info: No valid register-to-register paths exist for clock rd_clk" {  } {  } 0}