myfifo.tan.qmsg

来自「VERILOG HDL 实际工控项目源码」· QMSG 代码 · 共 27 行 · 第 1/5 页

{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[8\]~2441 " "Info: Node mydram:inst2\|d_out\[8\]~2441" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[8\]~2427 " "Info: Node mydram:inst2\|d_out\[8\]~2427" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[8\]~2404 " "Info: Node mydram:inst2\|d_out\[8\]~2404" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[0\]~2449 " "Info: Node mydram:inst2\|d_out\[0\]~2449" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[0\]~2435 " "Info: Node mydram:inst2\|d_out\[0\]~2435" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[0\]~2420 " "Info: Node mydram:inst2\|d_out\[0\]~2420" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[1\]~2448 " "Info: Node mydram:inst2\|d_out\[1\]~2448" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[1\]~2434 " "Info: Node mydram:inst2\|d_out\[1\]~2434" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[1\]~2418 " "Info: Node mydram:inst2\|d_out\[1\]~2418" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[2\]~2447 " "Info: Node mydram:inst2\|d_out\[2\]~2447" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[2\]~2433 " "Info: Node mydram:inst2\|d_out\[2\]~2433" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[2\]~2416 " "Info: Node mydram:inst2\|d_out\[2\]~2416" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[5\]~2444 " "Info: Node mydram:inst2\|d_out\[5\]~2444" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[5\]~2430 " "Info: Node mydram:inst2\|d_out\[5\]~2430" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[5\]~2410 " "Info: Node mydram:inst2\|d_out\[5\]~2410" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[3\]~2446 " "Info: Node mydram:inst2\|d_out\[3\]~2446" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[3\]~2432 " "Info: Node mydram:inst2\|d_out\[3\]~2432" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[3\]~2414 " "Info: Node mydram:inst2\|d_out\[3\]~2414" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}