myfifo.tan.qmsg

VERILOG HDL 实际工控项目源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 14 17:17:30 2004 " "Info: Processing started: Thu Oct 14 17:17:30 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off myfifo -c myfifo " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off myfifo -c myfifo" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[11\]~2438 " "Info: Node mydram:inst2\|d_out\[11\]~2438" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[11\]~2424 " "Info: Node mydram:inst2\|d_out\[11\]~2424" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "mydram:inst2\|d_out\[11\]~2398 " "Info: Node mydram:inst2\|d_out\[11\]~2398" {  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}  } { { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } } { "E:/FPGApro/mydram.v" "" "" { Text "E:/FPGApro/mydram.v" 77 -1 0 } }  } 0}