myfifo.eda.qmsg

来自「VERILOG HDL 实际工控项目源码」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 14 17:17:35 2004 " "Info: Processing started: Thu Oct 14 17:17:35 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --import_settings_files=off --export_settings_files=off myfifo -c myfifo " "Info: Command: quartus_eda --import_settings_files=off --export_settings_files=off myfifo -c myfifo" {  } {  } 0}
{ "Info" "IBASEO_DONE_HDL_SDO_GENERATION" "myfifo.vo myfifo_v.sdo E:/FPGApro/simulation/modelsim/ simulation " "Info: Generated files myfifo.vo and myfifo_v.sdo in directory E:/FPGApro/simulation/modelsim/ for EDA simulation tool" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 14 17:17:37 2004 " "Info: Processing ended: Thu Oct 14 17:17:37 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}