myfifo_cmp.qrpt

VERILOG HDL 实际工控项目源码

[||Compilation Report||Timing Analyzer||Clock Hold: 'g_clk']
COLUMN_WIDTHS=254L,168L,156L,82L,68L,194L,194L,180L,
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Compilation Report||Timing Analyzer||Clock Setup: 'we']
COLUMN_WIDTHS=64L,312L,546L,498L,82L,68L,201L,187L,173L,
OUTPUT_SECTION=1
PAGE_ORIENTATION=0